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SPCA717A
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
237 NOV. 11, 2002
Preliminary Version: 0.1
6.4.3. Slave mode
Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are inputs
that are registered on the rising edge of CLOCK. The horizontal
counter is incremented on the rising edge of CLOCK. Two clock
cycles after falling edge of HSYNC*, the counter is reset to one,
indicating the start of a new line. The vertical counter is
incremented on the falling edge of HSYNC*. A falling edge of
VSYNC* resets it to one, indicating the start of a new field. A
falling edge of VSYNC* occurring within ±1/4 of a scan line from
the falling edge of HSYNC* cycle time (line time) indicates the
beginning of
Field 1
.
A falling edge of VSYNC* occurring within
±1/4 scan line from the mid-point of the line indicates the
beginning of Field 2.
The operating mode (NTSC/PAL) can be programmed with the
MODEA and MODEB bits when the SETMODE (MASTER pin) bit
is set high. Alternatively, when SETMODE is low, the mode is
automatically detected in slave mode. For example, 525-line
operation is assumed, 625-line operation is detected by the
number of HSYNC* edges between VSYNC* edges. The
frequency of operation (CCIR-601) for both PAL and NTSC is
detected by counting the number of clocks per line. The pixel
rate is assumed to be 13.5 MHz, ±1 count which is detected in
between two successive falling edges of HSYNC*.
6.4.4. Burst blanking
For NTSC, color burst information is automatically disabled on
scan lines 1-9 and 264-272, inclusive. (SMPTE line numbering
convention.) For PAL-B, D, G, H, I , Nc color burst information is
automatically disabled on scan lines 1-6, 310-318, and 623-625,
inclusive, for fields 1, 2, 5, and 6. During fields 3, 4, 7, and 8,
color burst information is disabled on scan lines 1-5, 311-319, and
622-625, inclusive.
6.5. Vertical Blanking Intervals
For NTSC, scan lines 1-9 and 263-272, inclusive, are always
blanked. There is no setup on scan lines 10-21 and 273-284
inclusive. All displayed lines in the vertical blanking interval
(10-21 and 273-284 for interlaced NTSC; 7-13 and 320-335 for
interlaced PAL-B, D, G, H, I) are forced to blank. For PAL-B, D, G,
H, I, scan lines 1-6, 311-318, and 624-625, inclusive, during fields
1, 2, 5, and 6, are always blanked. During fields 3, 4, 7, and 8,
scan lines 1-5, 311-319, and 624-625, inclusive, are always
blanked.
6.6. Digital Processing
Once the input data is converted into internal YUV format, the UV
components are low -pass filtered with a filter. The Y and filtered
UV components are up-sampled to CLK frequency by a digital
filter.
6.7. Subcarrier Generation
To maintain a synchronous sub-carrier relative to HSYNC*, the
sub-carrier phase is reset every frame for NTSC and every 8 fields
for PAL. The SCA phase is non-zero and depends upon the
clock frequency and the video format.
For a perfect clock input, The burst frequency is 4.43361875 MHz
for PAL-B, D, G, H, I, 3.57561149MHz for PAL-M, 3.58205625MHz
for PAL-Nc (Argentina), 3.579545 MHz for NTSC interlaced.
6.8. Power-Down Mode
In power-down mode (SLEEP pin set to 1), the internal clock is
stopped and also an internal reset is forced and the DACs are
powered down. When returned low , the device starts from a
reset state (horizontal and vertical counters = 0, which is the start
of VSYNC in Field 1).
Содержание PV420S
Страница 1: ...SERVICE MANUAL PV420S WWW BBK RU ...
Страница 72: ... 69 CXD3068Q Block Diagram ...
Страница 73: ... 70 CXD3068Q Pin Configuration ...
Страница 122: ... 119 CXD3068Q Timing Chart 1 3 ...
Страница 123: ... 120 CXD3068Q Timing Chart 1 4 ...
Страница 124: ... 121 CXD3068Q Timing Chart 1 5 ...
Страница 127: ... 124 CXD3068Q Timing Chart 1 16 CAV W mode EPWM 1 LPWR 0 Timing Chart 1 17 CAV W mode EPWM LPWR 1 ...
Страница 129: ... 126 CXD3068Q Timing Chart 2 1 ...
Страница 130: ... 127 CXD3068Q Block Diagram 2 2 ...
Страница 131: ... 128 CXD3068Q Timing Chart 2 3 ...
Страница 134: ... 131 CXD3068Q Timing Chart 2 6 ...
Страница 137: ... 134 CXD3068Q Fig 3 1 Disc Stop to Regular Playback in CLV W Mode CLV W Mode Fig 3 2 CLV W Mode Flow Chart ...
Страница 138: ... 135 CXD3068Q VCO C Mode Fig 3 3 Access Flow Chart Using VCO Control ...
Страница 140: ... 137 CXD3068Q Block Diagram 4 1 ...
Страница 143: ... 140 CXD3068Q Timing Chart 4 4 ...
Страница 147: ... 144 CXD3068Q Fig 4 6 a Auto Focus Flow Chart Fig 4 6 b Auto Focus Timing Chart ...
Страница 148: ... 145 CXD3068Q Fig 4 7 a 1 Track Jump Flow Chart Fig 4 7 b 1 Track Jump Timing Chart ...
Страница 149: ... 146 CXD3068Q Fig 4 8 a 10 Track Jump Flow Chart Fig 4 8 b 10 Track Jump Timing Chart ...
Страница 150: ... 147 CXD3068Q Fig 4 9 a 2N Track Jump Flow Chart Fig 4 9 b 2N Track Jump Timing Chart ...
Страница 151: ... 148 CXD3068Q Fig 4 10 a Fine Search Flow Chart Fig 4 10 b Fine Search Timing Chart ...
Страница 152: ... 149 CXD3068Q Fig 4 11 a M Track Move Flow Chart Fig 4 11 b M Track Move Timing Chart ...
Страница 157: ... 154 CXD3068Q Fig 4 15 CD TEXT Data Timing Chart ...
Страница 162: ... 159 CXD3068Q Fig 5 3a Fig 5 3b ...
Страница 176: ... 173 CXD3068Q Fig 5 26a Servo HighBooster Characteristics FCS TRK MCK 128Fs HBST1 0 HBST1 1 HBST0 0 HBST1 1 HBST0 1 ...
Страница 177: ... 174 CXD3068Q Fig 5 26b Servo LowBooster1 Characteristics FCS TRK MCK 128Fs LB1S1 0 LB1S1 1 LB1S0 0 LB1S1 1 LB1S0 1 ...
Страница 178: ... 175 CXD3068Q Fig 5 26c Servo LowBooster2 Characteristics FCS TRK MCK 128Fs LB2S1 0 LB2S1 1 LB2S0 0 LB2S1 1 LB2S0 1 ...
Страница 196: ... 193 CXD3068Q Description of Data Readout ...
Страница 200: ... 197 CXD3068Q ...
Страница 201: ... 198 CXD3068Q ...
Страница 202: ... 199 CXD3068Q ...
Страница 203: ... 200 CXD3068Q SLD Servo fs 345Hz Note Set the MSB bit of the K02 and K04 coefficients to 0 HPTZC Auto Gain fs 88 2kHz ...
Страница 207: ... 204 CXD3068Q Package Outline Unit mm ...
Страница 208: ...This data sheet has been made from recycled paper to help protect the environment 205 ...