Basler A400K, Руководство пользователя

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Camera Interface
2-28 Basler A400k
DRAFT
2.5.7 Video Data Output for the A404k
Depending on the video data output mode selected, A404k cameras output pixel data in either a
4 tap 10 bit, a 4 tap 8 bit or an 8 tap 8 bit video data stream.
2.5.7.1 4 Tap 10 Bit and 4 Tap 8 Bit Output Modes
In 4 tap 10 bit mode, on each clock cycle, the camera transmits data for four pixels at 10 bit depth,
a frame valid bit and a line valid bit. In 4 tap 8 bit mode, on each clock cycle, the camera transmits
data for four pixels at 8 bit depth, a frame valid bit and a line valid bit. The assignment of the bits
is shown in Tables
2-8 and 2-9 .
In 10 bit mode, all bits of data output from each 10-bit ADC are transmitted. In 8 bit mode, the two
least significant bits output from each ADC are dropped and the 8 most significant bits of data per
pixel are transmitted.
The video data output sequence for an A404k camera operating in 4 tap 10 bit or 4 tap 8 bit output
mode is similar to the output sequence of an A403k camera operating in 4 tap 10 bit or 4 tap 8 bit
output mode. Refer to Section
2.5.6 and Figures 2-10 and 2-11 for a description of the A403k
video data output sequence.
2.5.7.2 8 Tap 8 Bit Output Mode
In 8 tap output mode, on each clock cycle, the camera transmits data for eight pixels at 8 bit depth,
a frame valid bit and a line valid bit. The assignment of the bits is shown in Tables
2-8 , 2-9 and 2-
10 .
The pixel clock is used to time data sampling and transmission. As shown in Figures 2-12 and 2-
13 , the camera samples and transmits data on each rising edge of the pixel clock.
The frame valid bit indicates that a valid frame is being transmitted. The line valid bit indicates that
a valid line is being transmitted. Pixel data is only valid when the frame valid bit and the line valid
bit are both high.
The image has a maximum size of 2352 x 1726 pixels. Pixels are transmitted at a pixel clock
frequency of 50 MHz over the Camera Link X, Y, and Z transmitters. With each clock cycle, eight
pixels are transmitted in parallel at a depth of 8 bits. Therefore, one line takes a maximum of 294
clock cycles to be transmitted.
The image is transmitted line by line from top left to bottom right. Frame Valid (FVAL) and Line
Valid (LVAL) mark the beginning and duration of frame and line.
L
The data sequence outlined below, along with Figures 2-12 and 2-13 , describe what
is happening at the inputs to the Camera Link transmitters in the camera.
Note that the timing used for sampling the data at the Camera Link receivers in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which let you select
either rising edge or falling edge sampling. Please consult the data sheet for the re-
ceiver that you are using for specific timing information.