Basler A400K, Руководство пользователя

Страница: 40 / 176

Camera Interface
2-24 Basler A400k
DRAFT
2.5.6 Video Data Output for the A403k
Depending on the video data output mode selected, A403k cameras output pixel data in either a
4 tap 10 bit, or a 4 tap 8 bit video data stream.
In 4 tap 10 bit mode, on each clock cycle, the camera transmits data for four pixels at 10 bit depth,
a frame valid bit and a line valid bit. In 4 tap 8 bit mode, on each clock cycle, the camera transmits
data for four pixels at 8 bit depth, a frame valid bit and a line valid bit. The assignment of the bits
is shown in Tables
2-6 and 2-7 .
The pixel clock is used to time data sampling and transmission. As shown in Figures 2-10 and 2-
11 , the camera samples and transmits data on each rising edge of the pixel clock.
The frame valid bit indicates that a valid frame is being transmitted. The line valid bit indicates that
a valid line is being transmitted. Pixel data is only valid when the frame valid bit and the line valid
bit are both high.
The image has a maximum size of 2352 x 1726 pixels. Pixels are transmitted at a pixel clock
frequency of 50 MHz over the Camera Link X and Y transmitters. With each clock cycle, four pixels
are transmitted in parallel at a depth of 10 or 8 bits. Therefore, one line takes a maximum of 588
clock cycles to be transmitted.
The image is transmitted line by line from top left to bottom right. Frame Valid (FVAL) and Line
Valid (LVAL) mark the beginning and duration of frame and line.
In 10 bit mode, all bits of data output from each 10-bit ADC are transmitted. In 8 bit mode, the two
least significant bits output from each ADC are dropped and the 8 most significant bits of data per
pixel are transmitted.
Video Data Sequence for the A403k
When the camera is not transmitting valid data, the frame valid and line valid bits sent on each
cycle of the pixel clock will be low. The camera can begin capturing a new frame while it is sending
data for a previously captured frame. It can also capture a frame and then send it before beginning
capture of a new frame. When frame valid becomes high, the camera starts to send valid data:
• On the pixel clock cycle where frame data transmission begins, the frame valid bit will
become high. 24 pixel clocks (480 ns) later, the line valid bit will become high.
• On the pixel clock cycle where data transmission for line one begins, the line valid bit will
become high. Four data streams, D0, D1, D2 and D3 are transmitted in parallel during this
clock cycle. On this clock cycle, data stream D0 will transmit data for pixel one in line one.
Data stream D1 will transmit data for pixel two in line one. Data stream D2 will transmit data
for pixel three in line one. And data stream D3 will transmit data for pixel four in line one.
Depending on the video data output mode selected, the pixel data will be at either 10 bit or 8
bit depth.
• On the next cycle of the pixel clock, the line valid bit will be high. On this clock cycle, data
stream D0 will transmit data for pixel five in line one. Data stream D1 will transmit data for
L
The data sequence outlined below, along with Figures 2-10 and 2-11 , describe what
is happening at the inputs to the Camera Link transmitters in the camera.
Note that the timing used for sampling the data at the Camera Link receivers in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which let you select
either rising edge or falling edge sampling. Please consult the data sheet for the re-
ceiver that you are using for specific timing information.