96
ATmega103(L)
0945G–09/01
Figure 67.
Port E Schematic Diagram (Pin PE1)
Figure 68.
Port E Schematic Diagram (Pin PE2)
DA
TA
B
U
S
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PE2
AC+
TO COMPARATOR
WP:
WD:
RL:
RP:
RD:
WRITE PORTE
WRITE DDRE
READ PORTE LATCH
READ PORTE PIN
READ DDRE
DDE2
PORTE2
RL
RP