AT32F413
Series Reference Manual
2022.06.27
Page 51
Rev 2.00
a HEXT clock failure occurs. This bit can also be set. When
the HICK is used as the sytem clock, this bit cannot be
cleared.
0: Disabled
1: Enabled
4.3.2
Clock configuration register (CRM_CFG)
Accessible: 0 to 2 wait states, word, half-word and byte. 1 or 2 wait states are inserted only when the
access occurs during a clock source switch.
Bit
Name
Reset value
Type
Description
Bit 31
PLLRANGE
0x0
rw
PLL clock output range
0: PLL output
≦
72 MHz
1: PLL output > 72 MHz
Bit 26: 24
CLKOUT_SEL 0x0
rw
Clock output selection
CLKOUT_SEL[3] is in bit 16 of the CRM_MISC1 register.
0000: Not clock output
0001: Reserved
0010: LICK
0011: LEXT
0100: SCLK
0101: HICK
0110: HEXT
0111: PLL/2
1100: PLL/4
1101: USB
1110: ADC
Bit 27
Bit 23: 22
USBDIV
0x0
rw
USB frequency division factor
After being divided, the PLL clock is used as USB clock.
000: PLL clock divided by 1.5 to be USB clock
001: PLL clock is directly to be USB clock.
010: PLL clock divided by 2.5 to be USB clock
011: PLL clock divided by 2 to be USB clock
100: PLL clock divided by 3.5 to be USB clock
101: PLL clock divided by 3 to be USB clock
110: PLL clock divided by 4 to be USB clock
111: PLL clock divided by 4 to be USB clock
Bit 30: 29
Bit 21: 18
PLLMULT
0x00
rw
PLL multiplication factor { Bit 30: 29, Bit 21: 18}
000000: PLL output x 2 000001: PLL output x 3
000010: PLL output x 4 000011: PLL output x 5
……
001100: PLL output x 14 001101: PLL output x 15
001110: PLL output x 16 001111: PLL output x 16
010000: PLL output x 17 010001: PLL output x 18
010010: PLL output x 19 010011: PLL output x 20
……
111110: PLL output x 63 111111: PLL output x 64
Note: PLLRANGE bit has to be configured along with PLL
output.
Bit 17
PLLHEXTDIV
0x0
rw
HEXT division selection for PLL entry clock
0: HEXT is not divided
1: HEXT is divided according to the setting of HEXTDIV.
Bit 16
PLLRCS
0x0
rw
PLL entry clock select
0: HICK clock divided (4MHz) to be PLL entry clock