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DECA User Manual

www.terasic.com

May 22, 2015

CLASS I

DDR3_CK_p

PIN_D18

Clock p for DDR3

Differential 1.5-V SSTL

Class I

DDR3_CS_n

PIN_F22

DDR3 Chip Select

SSTL-15 Class I

DDR3_DM[0]

PIN_N19

DDR3 Data Mask[0]

SSTL-15 Class I

DDR3_DM[1]

PIN_J15

DDR3 Data Mask[1]

SSTL-15 Class I

DDR3_DQ[0]

PIN_L20

DDR3 Data[0]

SSTL-15 Class I

DDR3_DQ[1]

PIN_L19

DDR3 Data[1]

SSTL-15 Class I

DDR3_DQ[2]

PIN_L18

DDR3 Data[2]

SSTL-15 Class I

DDR3_DQ[3]

PIN_M15

DDR3 Data[3]

SSTL-15 Class I

DDR3_DQ[4]

PIN_M18

DDR3 Data[4]

SSTL-15 Class I

DDR3_DQ[5]

PIN_M14

DDR3 Data[5]

SSTL-15 Class I

DDR3_DQ[6]

PIN_M20

DDR3 Data[6]

SSTL-15 Class I

DDR3_DQ[7]

PIN_N20

DDR3 Data[7]

SSTL-15 Class I

DDR3_DQ[8]

PIN_K19

DDR3 Data[8]

SSTL-15 Class I

DDR3_DQ[9]

PIN_K18

DDR3 Data[9]

SSTL-15 Class I

DDR3_DQ[10]

PIN_J18

DDR3 Data[10]

SSTL-15 Class I

DDR3_DQ[11]

PIN_K20

DDR3 Data[11]

SSTL-15 Class I

DDR3_DQ[12]

PIN_H18

DDR3 Data[12]

SSTL-15 Class I

DDR3_DQ[13]

PIN_J20

DDR3 Data[13]

SSTL-15 Class I

DDR3_DQ[14]

PIN_H20

DDR3 Data[14]

SSTL-15 Class I

DDR3_DQ[15]

PIN_H19

DDR3 Data[15]

SSTL-15 Class I

DDR3_DQS_n[0]

PIN_L15

DDR3 Data Strobe n[0]

Differential 1.5-V SSTL

Class I

DDR3_DQS_n[1]

PIN_K15

DDR3 Data Strobe n[1]

Differential 1.5-V SSTL

Class I

DDR3_DQS_p[0]

PIN_L14

DDR3 Data Strobe p[0]

Differential 1.5-V SSTL

Class I

DDR3_DQS_p[1]

PIN_K14

DDR3 Data Strobe p[1]

Differential 1.5-V SSTL

Class I

DDR3_ODT

PIN_G22

DDR3 On-die Termination

SSTL-15 Class I

DDR3_RAS_n

PIN_D22

DDR3 Row Address Strobe

SSTL-15 Class I

DDR3_RESET_n

PIN_U19

DDR3 Reset

SSTL-15 Class I

DDR3_WE_n

PIN_E22

DDR3 Write Enable

SSTL-15 Class I

3.4.7

The DECA supports a 512M-bit serial NOR flash device for non-volatile storage, user data and
program. This device has a 4-bit data interface and uses 3.3V CMOS signaling standard.
Connections between MAX 10 FPGA and Flash are shown in

Figure 3-21

Table 3-12

shows the

DDR3 interface pin assignments

Содержание DECA

Страница 1: ...DECA User Manual 1 www terasic com May 22 2015 ...

Страница 2: ...r 3 Using the DECA Board 10 3 1 Configuration of MAX 10 FPGA on DECA 10 3 2 Board Status Elements 16 3 3 Clock Circuitry 17 3 4 Peripherals Connected to the FPGA 18 Chapter 4 DECA System Builder 44 4 1 Introduction 44 4 2 General Design Flow 44 4 3 Using DECA System Builder 45 Chapter 5 RTL Example Codes 51 5 1 Breathing LED 51 5 2 User IO and CLOCK 53 5 3 Humidity and Temperature Measure 56 5 4 P...

Страница 3: ...est by Nios II 87 Chapter 7 Advanced NIOS Based Example Codes 91 7 1 HDMI Video Audio TX 91 7 2 Gesture Light Sensor 96 7 3 Ethernet Socket server 100 7 4 Micro SD Card file system read 108 7 5 Audio 112 7 6 USB Port Interface 114 Chapter 8 Programming the Configuration Flash Memory 120 8 1 Internal Configuration 120 8 2 Factory Default Dual Boot Image 122 8 3 Using Dual Compressed Images 122 Chap...

Страница 4: ...ve design protection features integrated ADCs and hardware to implement the Nios II 32 bit microcontroller IP MAX10 devices are ideal solution for system management I O expansion communication control planes industrial automotive and consumer applications The DECA development board is equipped with high speed DDR3 memory video and audio capabilities Ethernet networking and much more that promise m...

Страница 5: ...porting materials associated with DECA including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http cd deca terasic com 1 1 3 3 G Ge et tt ti in ng g H He el lp p Here are the addresses where you can get help if you encounter any problems Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email university a...

Страница 6: ... of the DECA Board 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s Figure 2 1 shows a photograph of the board It depicts the layout of the board and indicates the location of the connectors and key components Figure 2 1 DECA development board top view ...

Страница 7: ...a bus 64MB QSPI Flash Micro SD card socket Two CapSense buttons Two push buttons Two slide switches Eight blue user LEDs Three 50MHz clock sources from the clock generator 24 bit CD quality audio CODEC with line in line out jacks HDMI TX incorporates HDM v1 4 features including 3D video supporting One 10 100 Mbps Ethernet PHY with RJ45 connector One USB 2 0 PHY with mini USB type AB connector One ...

Страница 8: ...IOs 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE EC CA A B Bo oa ar rd d Figure 2 3 is the block diagram of the board All the connections are established through the MAX 10 FPGA device to provide maximum flexibility for users Users can configure the FPGA to implement any system design Figure 2 3 Block diagram of DECA ...

Страница 9: ...nnector M Me em mo or ry y D De ev vi ic ce e 512MB DDR3 SDRAM 16 bit data bus 64MB QSPI Flash Micro SD card socket C Co om mm mu un ni ic ca at ti io on n 10 100 Mbps Ethernet PHY with RJ45 connector USB 2 0 PHY with mini USB type AB connector C Co on nn ne ec ct to or rs s Two 46 pin BBB expansion headers Two MAX 10 FPGAADC SMA inputs D Di is sp pl la ay y HDMI TX incorporates HDM v1 4 features ...

Страница 10: ... BBB expansion header S Sw wi it tc ch he es s B Bu ut tt to on ns s a an nd d I In nd di ic ca at to or rs s 2 push buttons 2 slide switches 8 blue user LEDs S Se en ns so or rs s One proximity ambient lighter sensor One humidity and temperature sensor One temperature sensor One accelerometer P Po ow we er r 5V DC input ...

Страница 11: ...t are used for JTAG configuration with a download cable in the Quartus II software programmer 2 Internal configuration configuration using internal flash Before internal configuration you need to program the configuration data into the configuration flash memory CFM which provides non volatile storage for the bit stream The information is retained within CFM even if the DECA board is turned off Wh...

Страница 12: ... 3 1 Path of the JTAG chain Configure the FPGA in JTAG Mode The following shows how the FPGA is programmed in JTAG mode step by step 1 Open the Quartus II programmer and click Auto Detect as circled in Figure 3 2 Figure 3 2 Detect FPGA device in JTAG mode ...

Страница 13: ...vice associated with the board as circled in Figure 3 3 Figure 3 3 Select 10M50DAES device 3 FPGA is detected as shown in Figure 3 4 Figure 3 4 FPGA detected in Quartus programmer 4 Right click on the FPGA device and open the sof file to be programmed as highlighted in ...

Страница 14: ...DECA User Manual 13 www terasic com May 22 2015 Figure 3 5 Figure 3 5 Open the sof file to be programmed into the FPGA device 5 Select the sof file to be programmed as shown in Figure 3 6 ...

Страница 15: ...terasic com May 22 2015 Figure 3 6 Select the sof file to be programmed into the FPGA device 6 Click Program Configure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 7 ...

Страница 16: ...n data to be written to CFM will be part of the programmer object file pof This configuration data is automatically loaded from the CFM into the MAX 10 devices when the board is powered up Please refer to Chapter 8 Programming the Configuration Flash Memory CFM for the basic programming instruction on the configuration flash memory CFM ...

Страница 17: ...control there are 4 indicators which can indicate the board status See Figure 3 9 please refer the details in Table 3 1 Figure 3 9 LED Indicators on DECA Table 3 1 LED Indicators Board Reference LED Name Description D6 3 3V Power Illuminate when 3 3V power is active D8 CONF_DONE Illuminate when configuration data is loaded into MAX 10 device without error D5 JTAG_RX Illuminate during data is uploa...

Страница 18: ...e used as clock sources for user logic One 25MHz clock signal is connected to the clock input of Gigabit Ethernet Transceiver One 24MHz clock signal is connected to the clock inputs of USB microcontroller of USB Blaster II One 19 2MHz clock signal is connected to the reference clock input of USB2 0 PHY transceiver chip The other 50MHz clock signal is connected to MAX CPLD of USB Blaster II One 10M...

Страница 19: ...K1_50 PIN_M8 50 MHz clock input 2 5V MAX10_CLK2_50 PIN_P11 50 MHz clock input 3 3V DDR3_CLK_50 PIN_N15 50 MHz clock input 1 5V ADC_CLK_10 PIN_M9 10 MHz clock input 2 5V 3 3 4 4 P Pe er ri ip ph he er ra al ls s C Co on nn ne ec ct te ed d t to o t th he e F FP PG GA A This section describes the interfaces connected to the FPGA User can control or monitor different interfaces with user logic from t...

Страница 20: ...trigger input on all I O pins A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity especially for signal with slow edge rate and act as switch debounce in Figure 3 12 for the push buttons connected Figure 3 11 Connections between the push buttons and the MAX 10 FPGA Pushbutton released Pushbutton depressed Before Debouncing Schmitt Trigger Debounced Figur...

Страница 21: ...3 13 Connections between the CapSense buttons and the MAX 10 FPGA There are two slide switches connected to the FPGA as shown in Figure 3 14 These switches are used as level sensitive data inputs to a circuit Each switch is connected directly and individually to the FPGA When the switch is set to the DOWN position towards the edge of the board it generates a low logic level to the FPGA When the sw...

Страница 22: ...en directly and individually by the MAX 10 FPGA driving its associated pin to a high logic level or low level to turn the LED on or off respectively Figure 3 15 shows the connections between LEDs and MAX 10 FPGA Table 3 3 Table 3 4 Table 3 5 and Table 3 6 list the pin assignment of user push buttons CapSense buttons switches and LEDs Figure 3 15 Connections between the LEDs and the Cyclone V SoC F...

Страница 23: ...Ds Signal Name FPGA Pin No Description I O Standard LED 0 PIN_C7 LED 0 1 2V LED 1 PIN_C8 LED 1 1 2V LED 2 PIN_A6 LED 2 1 2V LED 3 PIN_B7 LED 3 1 2V LED 4 PIN_C4 LED 4 1 2V LED 5 PIN_A5 LED 5 1 2V LED 6 PIN_B4 LED 6 1 2V LED 7 PIN_C5 LED 7 1 2V 3 4 2 P Po ow we er r M Mo on ni it to or r The DECA has implemented a power monitor chip to monitor the FPGA core power voltage and current Figure 3 16 sho...

Страница 24: ... 3 3 T Tw wo o 2 2x x2 23 3 E Ex xp pa an ns si io on n H He ea ad de er rs s The board has two 46 pin expansion headers The P8 header has 44 digital user pins connected directly to the MAX 10 FPGA the P9 header has 25 digital and 7 analog user pins connected to the MAX 10 FPGA The P9 header also comes with DC 5V VCC5 DC 3 3V VCC3P3 power pins The maximum power consumption allowed for a daughter c...

Страница 25: ...3 3 3V GPIO0_D 4 PIN_AA20 GPIO P8 Connection 0 4 3 3V GPIO0_D 5 PIN_AA19 GPIO P8 Connection 0 5 3 3V GPIO0_D 6 PIN_AB21 GPIO P8 Connection 0 6 3 3V GPIO0_D 7 PIN_AB20 GPIO P8 Connection 0 7 3 3V GPIO0_D 8 PIN_AB19 GPIO P8 Connection 0 8 3 3V GPIO0_D 9 PIN_Y16 GPIO P8 Connection 0 9 3 3V GPIO0_D 10 PIN_V16 GPIO P8 Connection 0 10 3 3V GPIO0_D 11 PIN_AB18 GPIO P8 Connection 0 11 3 3V GPIO0_D 12 PIN_...

Страница 26: ...IO P8 Connection 0 35 3 3V GPIO0_D 39 PIN_V14 GPIO P8 Connection 0 35 3 3V GPIO0_D 40 PIN_Y17 GPIO P8 Connection 0 35 3 3V GPIO0_D 41 PIN_W14 GPIO P8 Connection 0 35 3 3V GPIO0_D 42 PIN_U15 GPIO P8 Connection 0 35 3 3V GPIO0_D 43 PIN_R13 GPIO P8 Connection 0 35 3 3V GPIO1_D 0 PIN_Y5 GPIO P9 Connection 1 0 3 3V GPIO1_D 1 PIN_Y6 GPIO P9 Connection 1 1 3 3V GPIO1_D 2 PIN_W6 GPIO P9 Connection 1 2 3 3...

Страница 27: ... 2 5V 3 4 4 2 24 4 b bi it t A Au ud di io o C CO OD DE EC C The DECA offers high quality 24 bit audio via the Texas Instruments TLV320AIC3254 audio CODEC Encoder Decoder This chip on DECA supports line in and line out ports One of line in inputs is both connected to the FPGA ADC and the audio CODEC ADC it allows user to implement audio applications via the MAX 10 build in ADC The operational ampl...

Страница 28: ...dphone detect output 1 5V AUDIO_SCL_SS_n PIN_P20 I2C Clock SPI interface mode chip select signal 1 5V AUDIO_SDA_MOSI PIN_P21 I2C Data SPI interface mode serial data output 1 5V AUDIO_MISO_MFP4 PIN_N21 Serial data input General purpose input 1 5V AUDIO_SPI_SELECT PIN_N22 Control mode select pin 1 5V AUDIO_RESET_n PIN_M21 Reset signal 1 5V AUDIO_GPIO_MFP5 PIN_M22 General Purpose digital IO CLKOUT in...

Страница 29: ... FPGA Figure 3 19 Connection of SMA connectors to the FPGA 3 4 6 D DD DR R3 3 M Me em mo or ry y The board supports 512MB of DDR3 SDRAM comprising of one 16 bit DDR3 device The DDR3 devices shipped with this board are running at 300MHz with the soft IP of MAX 10 external memory interface solution Figure 3 20 shows the connections between the DDR3 and MAX 10 FPGA Table 3 11 shows the DDR3 interface...

Страница 30: ...DR3_A 7 PIN_U20 DDR3 Address 7 SSTL 15 Class I DDR3_A 8 PIN_Y20 DDR3 Address 8 SSTL 15 Class I DDR3_A 9 PIN_W22 DDR3 Address 9 SSTL 15 Class I DDR3_A 10 PIN_C22 DDR3 Address 10 SSTL 15 Class I DDR3_A 11 PIN_Y22 DDR3 Address 11 SSTL 15 Class I DDR3_A 12 PIN_N18 DDR3 Address 12 SSTL 15 Class I DDR3_A 13 PIN_V22 DDR3 Address 13 SSTL 15 Class I DDR3_A 14 PIN_W20 DDR3 Address 14 SSTL 15 Class I DDR3_BA...

Страница 31: ...DDR3_DQ 12 PIN_H18 DDR3 Data 12 SSTL 15 Class I DDR3_DQ 13 PIN_J20 DDR3 Data 13 SSTL 15 Class I DDR3_DQ 14 PIN_H20 DDR3 Data 14 SSTL 15 Class I DDR3_DQ 15 PIN_H19 DDR3 Data 15 SSTL 15 Class I DDR3_DQS_n 0 PIN_L15 DDR3 Data Strobe n 0 Differential 1 5 V SSTL Class I DDR3_DQS_n 1 PIN_K15 DDR3 Data Strobe n 1 Differential 1 5 V SSTL Class I DDR3_DQS_p 0 PIN_L14 DDR3 Data Strobe p 0 Differential 1 5 V...

Страница 32: ...V FLASH_DATA 3 PIN_P10 FLASH Data 3 3 3V FLASH_DCLK PIN_R12 FLASH Data Clock 3 3V FLASH_NCSO PIN_R10 FLASH Chip Enable 3 3V 3 4 8 E Et th he er rn ne et t The board supports 10 100 Mbps Ethernet transfer by an external Texas Instruments DP83620 PHY chip The DP838620 also provides flexibility by supporting both MII and RMII interfaces Figure 3 22 shows the connections between the MAX 10 FPGA Ethern...

Страница 33: ..._W2 MII transmit data 3 2 5V NET_RX_DV PIN_P4 GMII and MII receive data valid 2 5V NET_RX_ER PIN_V1 GMII and MII receive data valid 2 5V NET_RXD 0 PIN_U5 GMII and MII receive data 0 2 5V NET_RXD 1 PIN_U4 GMII and MII receive data 1 2 5V NET_RXD 2 PIN_R7 GMII and MII receive data 2 2 5V NET_RXD 3 PIN_P8 GMII and MII receive data 3 2 5V NET_RX_CLK PIN_T6 GMII and MII receive clock 2 5V NET_RESET_n P...

Страница 34: ...he Datasheets HDMI folder on the Kit System CD Table 3 14 lists the HDMI Interface pin assignments and signal names relative to the MAX 10 device Figure 3 23 Connection between the MAX 10 FPGA and HDMI transmitter Table 3 14 Pin Assignment of HDMI TX Signal Name FPGA Pin No Description I O Standard HDMI_TX_D0 PIN_C18 Video Data bus 1 8V HDMI_TX_D1 PIN_D17 Video Data bus 1 8V HDMI_TX_D2 PIN_C17 Vid...

Страница 35: ...I2C_SDA PIN_B15 I2C Data 1 8V HDMI_MCLK PIN_A7 Audio Reference Clock Input 1 8V HDMI_LRCLK PIN_A10 Left Right Channel Signal Input 1 8V HDMI_SCLK PIN_D12 I2S Audio Clock Input 1 8V HDMI_I2S0 PIN_A9 I2C Channel 0 Audio Data Input 1 8V HDMI_I2S1 PIN_A11 I2C Channel 1 Audio Data Input 1 8V HDMI_I2S2 PIN_A8 I2C Channel 2 Audio Data Input 1 8V HDMI_I2S3 PIN_B8 I2C Channel 3 Audio Data Input 1 8V 3 4 10...

Страница 36: ...utput signal 7 1 8V USB_NXT PIN_H12 ULPI NXT output signal 1 8V USB_DIR PIN_J13 ULPI DIR output signal 1 8V USB_STP PIN_J12 ULPI STP input signal 1 8V USB_CS PIN_J11 Active high chip select pin 1 8V USB_RESET_n PIN_E16 Reset pin used to reset all digital registers 1 8V USB_CLKIN PIN_H11 ULPI 60 MHz output clock 1 2V USB_FAULT_n PIN_D8 Fault input from USB power switch 1 2V 3 4 11 M MI IP PI I I In...

Страница 37: ...MD_n 2 PIN_T1 HS Differential MIPI Serial 2 Data Lane negative 2 5V MIPI_MD_p 3 PIN_N2 HS Differential MIPI Serial 3 Data Lane negative 2 5V MIPI_MD_n 3 PIN_N3 HS Differential MIPI Serial 3 Data Lane negative 2 5V MIPI_MC_p PIN_N5 HS Differential MIPI Serial Clock Strobe positive 2 5V MIPI_MC_n PIN_N4 HS Differential MIPI Serial Clock Strobe negative 2 5V MIPI_LP_MD_p 0 PIN_A4 LP single ended MIPI...

Страница 38: ... Se en ns so or r The DECA has a low power reflectance based infrared proximity and ambient light sensor Si1143 with I2C digital interface and programmable event interrupt output The Si1143 is an active optical reflectance proximity detector and ambient light sensor whose operational state is controlled through registers accessible through the I2C interface The host can command the Si1143 to initi...

Страница 39: ...and humidity and temperature sensor Table 3 18 Pin Assignment of Humidity and Temperature Sensor Signal Name FPGA Pin No Description I O Standard RH_TEMP_I2C_SCL PIN_Y10 I2C Clock for HDC1000 Sensor 3 3V RH_TEMP_I2C_SDA PIN_AA10 I2C Data for HDC1000 Sensor 3 3V RH_TEMP_DRDY_n PIN_AB9 Data ready input from HDC1000 Sensor 3 3V 3 4 14 T Te em mp pe er ra at tu ur re e S Se en ns so or r The DECA prov...

Страница 40: ...put chip secetc 3 3V 3 4 15 A Ac cc ce el le er ro om me et te er r S Se en ns so or r The board comes with a digital accelerometer sensor LIS2DH12 commonly known as G sensor This G sensor is a small thin ultra low power assumption 3 axis accelerometer with digital I2C SPI serial interface standard output The LIS2DH12 has user selectable full scales of 2g 4g 8g 16g and it is capable of measuring a...

Страница 41: ...le mode I2C communication enabled 0 SPI communication mode I2C disabled 1 2V G_SENSOR_SCLK PIN_B5 I2C serial clock SPI serial port clock 1 2V G_SENSOR_INT1 PIN_E8 Interrupt pin 1 1 2V G_SENSOR_INT2 PIN_D7 Interrupt pin 2 1 2V 3 4 16 M Mi ic cr ro o S SD D C Ca ar rd d S So oc ck ke et t The board supports Micro SD card interface with x4 data lines Through the load switches U25 U26 and voltage tran...

Страница 42: ...MD_DIR PIN_U22 Direction control for command bit CMDA CMDB 1 5V SD_D0_DIR PIN_T22 Direction control for DAT0A DAT0B 1 5V SD_D123_DIR PIN_U21 Direction control for DAT1A B DAT2A B and DAT3A B 1 5V SD_SEL PIN_P13 FPGA output SD card VCCIO select 3 3V SD_DAT 0 PIN_R18 Data bit 0 connected to FPGA 1 5V SD_DAT 1 PIN_T18 Data bit 1 connected to FPGA 1 5V SD_DAT 2 PIN_T19 Data bit 2 connected to FPGA 1 5...

Страница 43: ...www terasic com May 22 2015 management for FPGAs and SoCs Figure 3 31 shows the positions of Altera Enpirion regulators on DECA Figure 3 32 is the power tree of DECA Figure 3 31 The positions of Altera Enpirion regulators ...

Страница 44: ...DECA User Manual 43 www terasic com May 22 2015 Figure 3 32 The power tree of DECA ...

Страница 45: ...re prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are Board is damaged due to incorrect bank voltage setting or pin assignment Board is malfunctioned because of wrong device chosen declaration of pin location or direction is incorrect or forgotten Performance degradation due to improper pin assignment 4...

Страница 46: ...ou can then download the sof file to the developmenet board via JTAG interface using the Qaurtus II programmer Figure 4 1 Design flow of building a project from the beginning to the end 4 4 3 3 U Us si in ng g D DE EC CA A S Sy ys st te em m B Bu ui il ld de er r This section provides the procedures in details on how to use the DECA System Builder Install and Launch the DECA System Builder The DEC...

Страница 47: ... 4 2 The GUI of DECA System Builder Enter Project Name Enter the project name in the circled area as shown in Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design entity Figure 4 3 Enter the project name ...

Страница 48: ...on pin direction and I O standard Figure 4 4 System configuration group BBB Header If user connect BBB daughter card to the BBB header on DECA the DECA System Builder can selection the desired pinout name as shown in Figure 4 5 There are two kind of pinout name One is the default and another is MODE 7 In default pinout the pinout name is the same as DECA schematic If MODE 7 the pinout name is the ...

Страница 49: ...is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field blank Project Setting Management The DECA System Builder also provides the option to load a setting or save user s current board configuration in cfg file as shown in Figure 4 6 ...

Страница 50: ... com May 22 2015 Figure 4 6 Project Settings Project Generation When users press the Generate button as shown in Figure 4 7 the DECA System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 ...

Страница 51: ...ject name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Project name sdc Synopsis Design Constraints file for Quartus II 5 Project name htm Pin Assignment Document Users can add custom logic into the project in Quartus II and compile the project to generate the SRAM Object File sof ...

Страница 52: ... to control the luminance of the LEDs by means of PWM Pulse Width Modulation scheme shown in Figure 5 1 The breathing behavior is similar to the human breath The LEDs are divided into 2 groups When one group of LEDs dims the light the other group of LEDs will light on and vice versa Note that users can control the LED luminance by changing the duty cycle of the PWM wave shown in Figure 5 2 A duty ...

Страница 53: ...on Batch File Demo batch file folder Demonstrations LedBreathe Batch file test bat FPGA configure file DECA sof Demonstration Setup Please make sure Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port J10 on the DECA board to the host PC Power on the DECA board Execute the demo batch file test bat under the folder Demonstrations LedB...

Страница 54: ...x6e Function Block Diagram Figure 5 3 is the function block diagram of this demonstration As LEDs LED0 LED7 and KEYs are active low the KEY status signals input to MAX10 can be directly output to the LED indicators When pressing a KEY the corresponding LED lights up Two SW signals are reversed by MAX10 and then output to LEDs Two 50MKZ clocks are divided by 50000000 in MAX10 to acquire 1HZ clocks ...

Страница 55: ...am of the User IO and CLOCK Design Tools Quartus II v15 0 Demonstration Source Code Project directory User_IO Bitstream used DECA_User_IO sof Demonstration Batch File Demo batch file folder User_IO demo_batch The directory includes the following files Batch file test bat ...

Страница 56: ...lights Switch SW1 to 0 LED3 doesn t light LED4 and LED5 blink with 1HZ Touch DECA B0 pade with finger LED6 lights Remove your finger from B0 LED6 doesn t light Touch DECA B1 pade with finger LED7 lights Remove your finger from B1 LED7 doesn t light Table 5 1 shows the details of each LED status Table 5 1 Status of LED Indicators Name Description LED0 Press KEY0 LED0 lights Release KEY0 LED0 doesn ...

Страница 57: ...MP module keeps sending master I2C timing to monitor HDC1000 to read real time temperature humidity value HDC1000 I2C Slave_address is 0x80 8 bit temperature and humidity values are saved respectively in Temperature register address 0x00 and Humidity register address 0x01 TP module here has no processing function it s just used to collect monitor signals for SingalTapeII IF SignalTap II is Altera ...

Страница 58: ...ct directory DECA_Humidity_Temperature Bitstream used DECA_Humidity_Temperature_Measurement sof Demonstration Batch File Demo batch file folder DECA_Humidity_Temperature demo The directory includes the following files Batch file test bat FPGA configuration file DECA_Humidity_Temperature_Measurement sof Demonstration Setup Quartus II v15 0 must be pre installed to the host PC Connect the DECA board...

Страница 59: ...perature 16 bits data and get 6cc4h 27844d it is current Temperature Register value Purple box is the actual temperature value refer to datasheet page14 actual temperature value Temperature Register 65536 165 40 27844 65536 165 40 30 1 30 5 5 4 4 P Po ow we er r M Mo on ni it to or r A power monitor IC INA230AIRGTR embedded on DECA board can monitor MAX10 real time current and power This IC can wo...

Страница 60: ...register values POWER_MONITOR module keeps sending I2C timing to read INA230 registers which including Bus_Voltage Register Address 0x02 Shunt_Voltage Register Address 0x01 Current Register Address 0x04 and Power Register Address 0x03 TP module here has the same function with the TP module in previous project it is used to collect signals to SignalTap II Figure 5 6 Block diagram of the Power Monit...

Страница 61: ...ltage 11 2 5uV 27 5uV The final results are Is VS RS 9 1mA P VB Is 1 2V 9 1mA 10 92mW For the second way suppose Current register 1LSB 0 1mA then CAL Register value 0 00512 Current_LSB RSHUNT 0 00512 0 1mA 0 003 17066 When setting CAL Register value to 17066 current register value is read about 92 Is 92 0 1mA P Power value can also be read in Power register Power register 1LSB 2 5mW and power actu...

Страница 62: ...e activated as shown in Figure 5 7 Click Signaltap II Start to run Signaltap II Calibration value and Current value will display on SignalTap II window Figure 5 7 Reading the register value of voltage and current via I2C interface 5 5 5 5 P Pr ro ox xi im mi it ty y A Am mb bi ie en nt t L Li ig gh ht t S Se en ns so or r There is a Proximity Ambient Light Sensor IC Si1143 with three LEDs on the b...

Страница 63: ...TA1 0x27 PS1_DATA0 0x26 PS2_DATA PS2_DATA1 0x29 PS2_DATA0 0x28 PS3_DATA PS3_DATA1 0x2b PS3_DATA0 0x2a In this demonstration we take the average of the three values as the distance value and send it to LEVEL_CAMP LEVEL_CAMP will output 8bit level to LED0 LED7 When the object is closest to the light sensor IC more LEDs LED0 LED7 light up On the contrary when object gets further to DECA board less LE...

Страница 64: ... board more LEDS light up When hand is closest to board all LEDs light up On the contrary when hand gets further to DECA board less LEDS light up when hand is far enough only LED0 lights up 5 5 6 6 G G S Se en ns so or r A 3 axis G sensor LIS2DH12TR embedded on DECA board can monitor DECA 3D gravitational acceleration Three axis are x y z Every axis angle value outputs by way of SPI interface This...

Страница 65: ...ing files Batch file test bat FPGA configuration file DECA_Gsensor sof D De em mo on ns st tr ra at ti io on n S Se et tu up p a an nd d I In ns st tr ru uc ct ti io on ns s Quartus II v15 0 must be pre installed to the host PC Connect the DECA board J10 to the host PC with a USB cable and install the USB Blaster II driver if necessary Plug the 5V adapter to DECA Board Place the DECA board horizon...

Страница 66: ... volume is very low Figure 5 10 shows the block diagram of Line In ADC on the DECA board The left channel of the audio jack is the audio input to a voltage translation circuit which later is being added 1 25V to the original signal The translated signal then goes to the built in ADC Finally the FPGA reads the digitalized 12 bit value from the ADC The output voltage and input voltage have the follo...

Страница 67: ...hich ADC channel value will be queried and the response interface is used to report the converted digital value associated with the specified ADC channel Figure 5 12 Interface of ADC control core only IP Figure 5 13 shows the timing diagram of command and response interfaces The responded digital value is stored in an unsigned 12 bit binary format with range from 0 to 4095 It is mapped to the volt...

Страница 68: ...elation between 12 bit output code and input voltage The 12 bit digital value 0 4095 represents 0 2 5V voltage input It is mapped to the input audio voltage from 1 25V to 1 2V Hence 0x800 is mapped to 0V audio input 0xFFF is mapped to 1 25V input audio and 0x00 is mapped to 1 25V input audio The absolute audio voltage is first ...

Страница 69: ...o the host PC Input audio into the Line In Jack J2 on the DECA board Power on the DECA board Execute the demo batch file test bat under the folder LineIn_ADC demo_batch The LEDs indicate the volume of input audio 5 5 8 8 H HD DM MI I T TX X Want to know more about HDMI We now introduce how to program the HDMI transmitter to generate video pattern and audio source The entire reference is composed i...

Страница 70: ...gned to transmit audio pattern to HDMI Transmitter the audio transmitting interface is using I2S in this demo Figure 5 15 Block Diagram of the HDMI TX Demonstration HDMI Transmitter ADV7513 Register Before you develop HDMI Transmitter setting the video format and audio frequency in Address 0x15 Register and the format of Address 0xAF Register could save you lots of developing time When we use 48KH...

Страница 71: ... Pattern Generator The module Video Pattern Generator copes with generating video patterns to be presented on the LCD monitor The pattern is composed in the way of 24 bit RGB 4 4 4 RGB888 per color pixel without sub sampling color encoding which corresponding to the parallel encoding format defined in Table 5 2 of the ADV7513 Hardware User s Guide as shown below Table 5 2 Display Modes of the HDMI...

Страница 72: ...batch folder Launch the configuration and program download process by double clicking test bat batch file This will configure the FPGA download the demo application to the board and start its execution After it s done the screen should look like the one shown in Figure 5 17 Figure 5 17 Launching the HDMI TX Demonstration using the demo_batch Folder Wait for a few seconds for the LCD monitor to pow...

Страница 73: ...DECA User Manual 72 www terasic com May 22 2015 Figure 5 18 The Video pattern used in the HDMI TX Demonstration ...

Страница 74: ...n There is a special capacitive touch sensor called CapSense on DECA board Capacitive touch sensors are user interface device that use the capacitance of the human body to detect the presence of a finger on or near a sensor Figure 6 1 shows the system block diagram of this reference design The capacitive touch sensor chip CY8CMBR3102 is controlled through I2C interface In this design an I2C OpenCo...

Страница 75: ...s only two sensors so only register bit CS0 Bit0 and CS1 Bit1 are used When CapSense is pressed the value of corresponding CS bit will be 1 The CS bit will be 0 once CapSense is released Figure 6 2 Register table of CapSense state Figure 6 3 shows the host reading CapSense button state through I2C Note the CY8CMBR3102 wakes up from the low power state upon address match but still sends NACK until ...

Страница 76: ...psense_NIOS sof Nios II Eclipse Capsense_NIOS Software Demonstration Batch File Demo Batch File Folder Capsense_NIOS demo_batch The demo batch includes the following files Demo batch file folder Capsense_NIOS demo_batch Batch file test bat test sh FPGA configure file Capsense_NIOS sof NIOS program Capsense elf Demonstration Setup Please make sure Quartus II and USB Blaster II driver are installed ...

Страница 77: ...mation which is collected by the built in temperature sensor on the DECA board can be converted into digital data by a 14 bit A D converter A Temp Controller is used by Nios II software to access the sensor s registers The C program will configure and read the registers and then calculates the centigrade degree The relative values are finally displayed onto the nios2 terminal window in order to le...

Страница 78: ... Batch File Demo Batch File Folder DECA _TEMP demo_batch The demo batch file includes the following files Batch File DECA_TEMP bat DECA _TEMP sh FPGA Configure File DECA _TEMP sof Nios II Program DECA _TEMP elf Demonstration Setup File Locations and Instructions Make sure Quartus II v15 0 and Nios II v15 0 are installed on your PC Power on the DECA board Connect USB Blaster II to the DECA board an...

Страница 79: ...Running results of the Temperature demonstration 6 6 3 3 P Po ow we er r M Mo on ni it to or r The Power Measurement demonstration illustrates how to measure the DECA power consumption based on the built in power measure circuit The power monitor chip INA230 is programmed through I2C protocol which is implemented in the C code The I2C pins from power monitor chip are connected to Qsys System Inter...

Страница 80: ...dated every two seconds Demonstration File Locations Hardware project directory DECA_Power_Monitor_Nios Bitstream used DECA_Power_Monitor_Nios sof Software project directory DECA_Power_Monitor_Nios software Demo batch file DECA_Power_Monitor_Nios demo_batch DECA_Power_Monitor_Nios bat DECA_Power_Monitor_Nios sh Demonstration Setup and Instructions Make sure Quartus II is installed on your PC Conne...

Страница 81: ...n ns so or r This demonstration illustrates steps to evaluate the performance of humidity and temperature sensor HDC1000 The HDC1000 is a fully integrated humidity and temperature sensor providing excellent measurement accuracy and long term stability Humidity and temperature results can be read out through the I2C compatible interface Figure 6 8 shows the block diagram of this demonstration In th...

Страница 82: ...on setting results in a different conversion time When Trigger the measurements operation should wait for the measurements to complete based on the conversion time Alternatively wait for the assertion of DRDYn In this demonstration a delay in I2C function is adopted to simplify the process System Requirements The following items are required for this demonstration DECA board x1 Demonstration File ...

Страница 83: ...ustrates how to use the digital accelerometer on the DECA board to measure the low power 3 axis LIS2DH12 in tilt sensing applications The acceleration measurement is implemented using the I2C SPI interfaces to measure the accelerations of X Y Z As the board is tilted the digital accelerometer detects the tilting movement The accelerations of 3 axis is displayed on the NIOS II console The LIS2DH12 ...

Страница 84: ...on File Locations Hardware project directory DECA_GSensor_Nios Bitstream used DECA_GSensor_Nios sof Software project directory DECA_GSensor_Nios software Demo batch file DECA_GSensor_Nios demo_batch DECA_GSensor_Nios bat Demonstration Setup and Instructions Make sure Quartus II is installed on your PC Connect USB cable to the DECA board and install the USB BlasterII driver if necessary ...

Страница 85: ...nd Result Information for the G sensor Demonstration 6 6 6 6 S SM MA A A AD DC C This demonstration shows how to use the built in ADC to measure the signal voltage from the SMA connector onboard The measured voltage is displayed in Nios II terminal Figure 6 13 shows the block diagram of SMA ADC on the DECA board The SMA input signal goes to the amplifier circuit and then to the build in ADC in MAX...

Страница 86: ...odular ADC core for the first SMA input in this demonstration Standard sequencer with Avalon MM sample storage is selected as the core to control the ADC Channel 0 in the first ADC is enabled because the first SMA input is connected to the ANAIN1 pin Figure 6 14 Settings of Altera Modular ADC Core The macro IOWR in Nios II program is used to access the controller s register file The following stat...

Страница 87: ...F 12 bit data The following statements calculate the input and output voltage values Vo_0 float value_0 4095 0 2 5 0 4095 mapping to 0 2 5V Vin_0 5 0 Vo_0 6 25 Vo_1 float value_1 4095 0 2 5 0 4095 mapping to 0 2 5V Vin_1 5 0 Vo_1 6 25 Demonstration Source Code Project directory SMA_ADC_NIOS Bit stream DECA sof Demonstration Batch File Demo batch file folder SMA_ADC_NIOS demo_batch Batch file test ...

Страница 88: ... provide temporary storage In this demonstration hardware and software designs are provided to illustrate how to perform DDR3 memory access in QSYS We describe how the Altera s DDR3 SDRAM Controller with UniPHY IP is used to access a DDR3 SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The DDR3 SDRAM controller handles the complex aspects of using ...

Страница 89: ...B of SDRAM Then it calls Nios II system function alt_dache_flush_all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal Altera DDR3 SDRAM Controller with UniPHY To use Alte...

Страница 90: ...emo_batch The demo batch file includes following files Batch File for USB Blaster II test bat test sh FPGA Configure File DECA sof Nios II Program DECA_DEMO elf Demonstration Setup Make sure Quartus II and Nios II are installed on your PC Power on the DECA board Use USB cable to connect PC and the DECA board J10 and install USB Blaster driver if necessary Execute the demo batch file test bat for U...

Страница 91: ...DECA User Manual 90 www terasic com May 22 2015 Figure 6 17 Display Progress and Result Information for the DDR3 Demonstration ...

Страница 92: ... t want to use RTL to develop HDMI Transmitter you can try C code to develop HDMI Transmitter we introduce a reference design for programming the HDMI transmitter to generate video pattern and audio sound The entire reference is composed into 2 parts RTL based hardware controller and C code main program running on NIOS II processor A set of pre built video patterns will be sent out through the HDM...

Страница 93: ...and Qsys on FPGA users can dump information out through JTAG UART The default resolution of video pattern is FULL HD generator 1920 1080p and it can be modified by adjusting the parameter of PLL and video pattern generator The module Video Pattern Generator copes with generating video patterns to be presented on the LCD monitor The pattern is composed in the way of 24 bit RGB 4 4 4 RGB888 per colo...

Страница 94: ...r up automatically when performing activities described above in this demonstration users can try to completely switch off the power of the LCD monitor and then switch on again Alternatively the user can try to unplug and then re plug the HDMI cable and wait for a reasonable time before the LCD monitor to complete its initialization process and start to sync with the HDMI transmitter Optimization ...

Страница 95: ...ect directory HDMI_TX_NIOS Nios II Eclipse HDMI_TX_NIOS Software Demonstration Batch File Demo batch file folder Demonstrations HDMI_TX_NIOS Batch file test bat FPGA configure file NIOS_HDMI_TX sof Nios II program HDMI_TX elf Demonstration Setup Make sure Quartus II and USB Blaster II driver are installed on your PC ...

Страница 96: ...batch file This will configure the FPGA and download the demo application to the board and start its execution A console terminal will be kept on the screen and the user can interact with the demo application through the console box After it s done the screen should look like the one shown in Figure 7 3 A tiny command line interface is provided to interact with the on board HDMI transmitter Note t...

Страница 97: ...th the on board HDMI transmitter 7 7 2 2 G Ge es st tu ur re e L Li ig gh ht t S Se en ns so or r DECA is able to provide advanced human machine interaction by gesture detection through the Proximity Sensing of 3 irLED Infrared Light Emitting Diode and the computing chip Si1143 First we introduces a reference design for programming the irLED The Si1143 is an active optical reflectance proximity de...

Страница 98: ...ure to shift one bit left from the original 7 bit I2C Slave to become 8 bit address value ex 0x01 0x02 JTAG UART module is used to let user dump information Si1143 will send out interrupt signal in specific situation so a PIO is needed to receive the interrupt signal from Si1143 Our demo shows 2 types of operations by press KEY 0 on DECA board to switch operation type Operation in type 1 Our defau...

Страница 99: ...ly then send out interrupt signal to NIOS when done reading and updating data We can apply this updating characteristic of timing difference and data changes of Proximity Sensing PS to achieve gesture detection As shown in Figure 7 7 indicates the gesture detection data in time domain of different gesture swipe For more details please refer to AN498 Designer s Guide for the Si114x or Si114xRev1_3 ...

Страница 100: ...ime domain Demonstration Source Code Project directory Gesture_Light_Sensor_NIOS Bit stream Light_Sensor sof Demonstration Batch File Demo batch file folder Gesture_Light_Sensor_NIOS demo_batch Batch File test bat test sh FPGA Configure File Light_Sensor sof NIOS Program Gesture_Test elf ...

Страница 101: ...t Figure 7 8 Left Swipe demonstration 7 7 3 3 E Et th he er rn ne et t S So oc ck ke et t s se er rv ve er r This design example shows a socket server using the sockets interface of the NicheStack TCP IP Stack Nios II Edition with MicroC OS II to serve socket connection to the DECA board The server can process continues to listen for commands on a TCP IP port and operates the DECA LEDs according t...

Страница 102: ...elated Qsys system The Qsys system used in this demo contains Nios II processor DDR3 memory JTAG UART timer Triple Speed Ethernet Scatter Gather DMA controller and other peripherals etc In the configuration page of the Altera Triple Speed Ethernet Controller users need to set the MAC interface as MII as shown in Figure 7 10 ...

Страница 103: ...hould be included as it is used to generate a 2 5MHz MDC clock for the PHY chip from the controller s source clock here a 100MHz clock source is expected to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100MHz and the desired MDC clock frequency is 2 5MHz so a host clock divisor of 40 shou...

Страница 104: ...3 www terasic com May 22 2015 Figure 7 11 MAC Options Configuration Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 7 12 click on generate ...

Страница 105: ...A User Manual 104 www terasic com May 22 2015 Figure 7 12 Qsys Builder Figure 7 13 shows the connections for programmable 10 100Mbps Ethernet operation via MII Figure 7 13 PHY connected to the MAC via MII ...

Страница 106: ...ides networking services to the application block where it contains the tasks for Socket Server Figure 7 14 Nios II Software Routine Architecture Finally the detail descriptions for Software flow chart of the Socket Server program are listed in below Firstly the Socket Server program initiates the MAC and net device then calls the get_mac_addr function to set the MAC addresses for the PHY Secondly...

Страница 107: ... demo setup and connections on DECA The Nios II processor is running NicheStack on the MicroC OS II RTOS Figure 7 15 System Principle Diagram Note your gateway should support DHCP because it uses DHCP protocol to request a valid IP from the Gateway or else you would need to reconfigure the system library to use static IP assignment Design Tools Quartus II v15 0 64 bit Demonstration Source Code Pro...

Страница 108: ...ed on the host PC Connect the USB cable from the USB Blaster II port J10 on the DECA board to the host PC Power on the DECA board Execute the demo batch file DECA_socket_server bat under the folder Demonstrations deca_socket_server demo_batch then the IP address and port number are assigned as shown below in Figure 7 16 Figure 7 16 Simple Socket Server To establish connection start the telnet clie...

Страница 109: ...ollowed by a return causes the corresponding LEDs D0 D7 to toggle on or off on the DECA board as shown below in Figure 7 18 Figure 7 18 Display Progress and Result Information for the Socket Server Demonstration 7 7 4 4 M Mi ic cr ro o S SD D C Ca ar rd d f fi il le e s sy ys st te em m r re ea ad d Many applications use a large external storage device such as SD Card or CF Card to store data ...

Страница 110: ...rd hardware The SD 4 bit protocol and FAT File System function are all implemented by Nios II software The software is stored at on chip memory Figure 7 19 Block diagram of the Micro SD demonstration Figure 7 20 shows the software stack of this demonstration The Nios PIO block provides basic IO functions to access hardware directly The functions are provided from Nios II system and the function pr...

Страница 111: ...no SD card found in the SD Card socket of the DECA board If users press KEY 1 on DECA board the program will perform the above process again Figure 7 20 Software of micro SD demonstration Demonstration Source Code Quartus Project directory SDCARD Nios II Eclipse SD_DEMO Software Demonstration Batch File Demo Batch File Folder SDCARD demo_batch The demo batch file includes following files Batch Fil...

Страница 112: ...r the batch file folder SDCARD demo_batch After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Copy SDCARD demo_batch test txt files to the root directory of the SD Card Insert the Micro SD Card into the SD Card socket of DECA as shown in Figure 7 21 Figure 7 21 Insert the Micro SD card into DECA Press KEY 1 on the DECA board to start r...

Страница 113: ... Qsys and Eclipse SW0 is used to configure this audio system which specify playing source to be Line in or Beep generation Figure 7 23 shows the block diagram of the Audio Player design There are hardware and software parts in the block diagram The software part stores the NiosII program in the on chip memory The software part is built by Eclipse written in the C programming language The hardware ...

Страница 114: ...connected to the MCLK pin of the audio chip Demonstration File Locations Hardware Project directory DECA_Audio Bit stream used DECA_Audio sof Software Project directory DECA_Audio software Demonstration Setup and Instructions Connect an audio source to the LINE IN port of the DECA board Connect a speaker or headset to LINE OUT port on the DECA board Load the bit stream into FPGA Load the software ...

Страница 115: ...nstrates USB Port Interface application on DECA board using the SLS USB20SR IP with ULPI interface In the demo the host PC can perform single word or multiple words read and write operation on the DECA board via USB interface Figure 7 25 shows the block diagram of the USB Port Interface system the SLS USB20SR has a ULPI interface which can connect with the ULPI PHY TUSB1210 and the PC can communic...

Страница 116: ...ts DMA access between USB20SR and the on chip memory which can increase the system efficiency and alleviate the Nios II burden on memory access And the DMA access is bidirectional which can perform write and read operation on the on chip memory The on chip memory address range for DMA access is 0x100BDCD to 0x1020F57 User can refer to the documents from the SLS website or IP installation package T...

Страница 117: ...USB Device Information Design Tools Quartus II v15 0 64 bit Demonstration Source Code Project directory Demonstrations deca_usb_ulpi Note the USB20SR IP license is Eval version so the sof file is time limited keep the usb blaster II cable connected during running ...

Страница 118: ... Please make sure Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port J10 on the DECA board to the host PC Power on the DECA board Execute the demo batch file test bat under the folder Demonstrations deca_usb_ulpi dem o_batch Input q to quit the info for USB20SR IP as Figure 7 27 shows Figure 7 27 Programming the SOF file Connect ano...

Страница 119: ...DECA User Manual 118 www terasic com May 22 2015 Figure 7 28 SLS USB 2 0 Device Execute the application file to make the Word or File Write and Read Verify operation as Figure 7 29 shows ...

Страница 120: ...rasic com May 22 2015 Figure 7 29 Word write and read Verfication Note using the on chip memory address range for DMA access from 0x100BDCD to 0x1020F57 and the file size for File Read and Write Verify should be within the range ...

Страница 121: ...t for 10M02 device consists of the following mode Dual Compressed Images configuration image is stored as image 0 and image 1 in the configuration flash memory CFM Single Compressed Image Single Compressed Image with Memory Initialization Single Uncompressed Image Single Uncompressed Image with Memory Initialization In dual compressed images mode you can use the BOOT_SEL pin to select the configur...

Страница 122: ... BOOT_SEL pin to determine which application configuration image to boot The BOOT_SEL pin setting can be overwritten by the input register of the remote system upgrade circuitry for the subsequent reconfiguration 2 If an error occurs the remote system upgrade feature reverts by loading the other application configuration image The following lists the errors that will cause the remote system upgrad...

Страница 123: ...Dual Boot 8 8 3 3 U Us si in ng g D Du ua al l C Co om mp pr re es ss se ed d I Im ma ag ge es s The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following mode Dual Compressed Images configuration image is stored as image 0 and image 1 in the configuration flash memory CFM Single Compressed Image This section will just introduce how to use MAX10 dev...

Страница 124: ...r of the remote system upgrade circuitry Reads information from the remote system upgrade circuitry Here we use a demonstration named Led Breathe as an example to add Altera Dual Configuration IP to the project 1 Open Quartus project and choose Tools Qsys to open new Qsys system wizard See Figure 8 4 Figure 8 4 Qsys Menu 2 Choose Library Basic Function Configuration and Programming Altera Dual Con...

Страница 125: ...Add Dual Boot IP 1 3 Click Finish to close the wizard and return to the window as shown in Figure 8 6 Figure 8 6 Add Dual Boot IP 2 4 Choose dual_boot_0 and rename it to dual_boot connect the clk and nreset to clk_0 clk and clk_0 clk_reset as shown in Figure 8 7 ...

Страница 126: ... Dual Boot IP 5 Click Generate tab and click Generate then pop a window as shown in Figure 8 8 Click Save it as dual_boot qsys and the generation start If there is no error in the generation the window will show successful as shown in Figure 8 9 Figure 8 8 Generate and save Qsys ...

Страница 127: ...ose and Finish to return to the window and add the dual boot qsys into the top file as shown in Figure 8 10 Figure 8 10 Input verilog Text 7 Add the dual_boot qip file to the project and save the project Secondly the project needs to be set before the compilation After adding dual IP successfully ...

Страница 128: ...Device to open Device windows shown in Figure 8 11 Figure 8 11 Device Window 2 Click Device and Pin Opinions to open the Device and Pin Opinions windows and in the Configuration tab Set the Configuration Scheme to Internal Configuration and the Configuration Mode to Dual Internal Images Check the Option of Generate compressed bitstreams shown in Figure 8 12 ...

Страница 129: ...tton on the toolbar to compile the project generate the new sof file 4 Use the same flow to add the Dual Configuration IP into DECA_Gsensor demo to generate the new sof file by internal configuration mode Finally So far we have successfully obtained two image sof files for dual boot demo according previous steps this section describes how to generate pof from sof files with the internal ...

Страница 130: ...e menu of Quartus II as shown in Figure 8 13 Figure 8 13 File menu of Quartus II 2 Select Programmer Object File pof from the Programming file type field in the dialog of Convert Programming Files 3 Choose Internal Configuration from the Mode filed 4 Browse to the target directory from the File name field and specify the name of output file 5 Click on the SOF data in the section of Input files to ...

Страница 131: ...f Convert Programming Files 6 Click Add File 7 Select the DECA sof of LedBreathe demo to be the sof data of Page_0 8 Click Add Sof Page to add Page_1 and click Add File Select the DECA_Gsensor sof of DECA_Gsensor demo to be the sof data of Page_1 as shown in Figure 8 15 ...

Страница 132: ...m the EPCS device with the pof file created in Quartus II Programmer 1 Choose Programmer from the Tools menu and the Chain cdf window will appear 2 Click Hardware Setup and then select the Arrow MAX 10 DECA as shown in Figure 8 16 3 Click Add File and then select the Dual_boot pof 4 Program the CFM device by clicking the corresponding Program Configure and Verify box as shown in Figure 8 17 5 Clic...

Страница 133: ...etup window Figure 8 17 Quartus II programmer window with pof file Now you can set the BOOT_SEL by SW2 you will find if you set BOOT_SEL 0 the Led Breathe functions would show Power down the board set BOOT_SEL 1 then Power on you would find the DECA Gsensor functions show ...

Страница 134: ...0 1 Initial Version Preliminary V0 2 Add Chapter 1 and Chapter 2 V0 3 Add Chapter 3 V0 4 Modify Chapter 3 V0 5 Add Chapter 4 and Chapter 5 V1 0 Add Chapter 6 and Chapter 7 V1 1 Add Chapter 8 V1 2 Modify Chapter 6 V1 3 Modify Chapter 8 9 9 2 2 C Co op py yr ri ig gh ht t S St ta at te em me en nt t Copyright 2015 Terasic Inc All rights reserved ...

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