DECA User Manual
87
www.terasic.com
May 22, 2015
Feed signals into the SMA connectors (J3 and J5) on the DECA board.
Power on the DECA board.
Execute the demo batch file “test.bat” under the batch file folder
SMA_ADC_NIOS\demo_batch.
Nios II terminal will display the voltage value of signals coming from the SMA connectors, as
shown in
Figure 6-15.
Figure 6-15 Screenshot of SMA-ADC demo
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Many applications use a high performance RAM, such as a DDR3 SDRAM, to provide temporary
storage. In this demonstration hardware and software designs are provided to illustrate how to
perform DDR3 memory access in QSYS. We describe how the Altera’s “DDR3 SDRAM Controller
with UniPHY” IP is used to access a DDR3-SDRAM, and how the Nios II processor is used to read
and write the SDRAM for hardware verification. The DDR3 SDRAM controller handles the
complex aspects of using DDR3 SDRAM by initializing the memory devices, managing SDRAM
banks, and keeping the devices refreshed at appropriate intervals.
System Block Diagram
Figure 6-16
shows the system block diagram of this demonstration. The system requires a 50 MHz
clock provided from the board. The DDR3 controller is configured as a 512 MB DDR3-300
