Aplex APC-3514, Руководство пользователя

Страница: 43 / 96

APC-3X14 User Manual 43
3.3.3 Advanced Chipset Features
3.3.3.1 DRAM Clock/Drive Control
When select to “BySPD”, the DRAM timing parameters are set according to DRAM SPD (Serial Presence
Detect). When disabled, one can manually set the DRAM timing parameters through the sub items below. Set to
“BySPD” if not sure.
3.3.3.2 CAS Latency Time
Controls the latency between the SDRAM Read command and the time data actually becomes available.
3.3.3.3 DRAM RAS# to CAS# Delay
Controls the latency between the DDR SDRAM active command and the read/write command.
3.3.3.4 DRAM RAS# Precharge
Controls the idle clocks after issuing a precharge command to the DDRSDRAM.
3.3.3.5 Precharge delay (tRAS)
Precharge Delay This setting controls the precharge delay, which determines the timing delay for DRAM
precharge.
3.3.3.6 System Memory Frequency
Allow to choose different frequency of memory module.
3.3.3.7 System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM at F0000h- FFFFFh, resulting in better system
performance. However, if any pro-gram writes data to this memory area, a system error may occur.
3.3.3.8 Video BIOS Cacheable