UG-1055
EVAL-ADAU1777Z User Guide
Rev. 0 | Page 14 of 25
TDM/I
2
S Stream
To use the serial audio outputs, connect the LRCLK, BCLK, and
SDATA lines to the appropriate MP pins on the evaluation
board. The connections are located on the J4 header. The silk
screen above the header helps to identify where to connect the
clocks and data (see Figure 42).
15
054-
042
Figure 42. Serial Audio Port
When the MP pins are connected, use
to set the
registers for the desired operation. In the
Output/Serial Port
tab, the
Serial Port Control
section contains settings that can
be changed to create the specific data stream desired. These
settings include
Serial Port FS
(sample rate),
Serial Port Mode
,
Serial Port Format
,
LRCLK/BCLK Mode
(slave or master),
BCLK Data-Change Edge
,
Bit Width in TDM mode
,
BCLK
Cycles per Channel
,
Data IO on LSB/MSB
,
Unused TDM
Outputs
,
LRCLK Mode
(as pulse or 50% duty cycle), and
LRCLK Polarity
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043
Figure 43. Serial Port Control
If using TDM mode, ensure that the appropriate TDM output
channels have been enabled in the
TDM Output Channel
section (see Figure 44).
1
505
4-
0
44
Figure 44. TDM Output Channel
Use the
Signal Routing
tab to route the core outputs, ADCs, or
serial inputs to the either of the two available serial output lines.
Ensure that
Output ASRC
is set to
Enabled
150
54-
04
5
Figure 45. Signal Routing
COMMUNICATIONS HEADER (J1)
J1 connects to the
USBi. More information
about the USBi can be found in the
application note.
The IC defaults to I
2
C mode; however, it can be put into SPI
control mode by pulling the CLATCH pin low three times.
SELF-BOOT
To use the
self-boot function, go to the
Hardware
Configuration
tab and add an
E2Prom
IC to the USBi interface
from the
Tree Toolbox
15054-
046
Figure 46. E2Prom