Analog Devices ADXL180 iMEMS, Руководство пользователя

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ADXL180
Rev. 0 | Page 6 of 56
Parameter
1
Symbol Min Typ Max Unit Test Conditions/Comments
ASYNCHRONOUS MODE TIMING
2
Message Transmission Period
Phase 2, Mode 0 t
PM0
456 μs ADIFX compatible
All Other Phases and Modes t
P
228 μs
Initialization State (Phase 1) t
I
100 ms
Device Data State (Phase 2) ms
Mode 0 t
DD0
4.10 ms
Mode 1 t
DD1
109 ms
Mode 2 t
DD2
109 ms
Mode 3 t
DD3
117 ms
Self-Test State (Phase 3)
Self-Test Time
3
t
ST
394 ms See Figure 26
Self-Test Interval t
STI
21.9 ms See Figure 26
Self-Test Cycle t
STC
65.7 ms See Figure 26
Auto-Zero Initialization State
(Phase 4)
t
AZ
14.94 sec
SYNCHRONOUS MODE TIMING
4
Message Transmission Period t
PS
N/A Determined by sync pulse, See Figure 12,
minimum t
PS
= t
SPD
+ t
STD
+ t
M
+ t
B
Initialization State1 (Phase 1) t
I
100 ms
Device Data State (Phase 2) ms
Mode 0 t
DD0s
9 × t
PS
ms
Mode 1 t
DD1s
480 × t
PS
ms
Mode 2 t
DD2s
480 × t
PS
ms
Mode 3 t
DD3s
512 × t
PS
ms
Self-Test State (Phase 3)
Self-Test Time
3
t
STS
1728 × t
PS
ms
Self-Test Interval t
STIS
96 × t
PS
ms
Self-Test Cycle t
STCS
288 × t
PS
ms
Auto-Zero Initialization State
(Phase 4)
t
AZs
65,535 × t
PS
sec
CLOCK
Period
2
t
CLK
1.05 1.0 0.95 μs f
CLK
= 1/t
CLK
PSRR
5
<1 LSB 8-bit LSB; test conditions: V
BP
− V
BN
= 7.00 V,
V
AC
= 500 mV p-p, 100 kHz to 1.1 MHz
POWER SUPPLY HOLDUP TIME 500 ns @ I
BUS
= I
SIG
THERMAL RESISTANCE, JUNCTION
TO CASE
θ
JC
30 °C/W
1
All parameters are specified using the application circuit shown in Figure 6. C
B
= 10 nF, C
VDD
= 100 nF.
2 All timing is driven from the on-chip master clock.
3 t
ST
and t
STS
are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode.
4
Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode.