ADXL180
Rev. 0 | Page 36 of 56
STC
PHASE 4
LOOP
CURRENT
I
IDLE
I
MOD
PHASE 3
t
ST
t
STC
t
STI
t
STI
t
STI
TIME
t
STI
07
54
4-
0
47
Figure 26. External Self-Test Control Timing
Internal Self-Test
The internal mode self-test applies an electrostatic force to
the sensor (simulating an acceleration force) and measures
the change in the sensor output value. A self-test cycle (t
STC
)
constitutes one activation and deactivation of the self-test
force. A self-test cycle is considered passed if the change in
the sensor output value falls within the expected minimum
and maximum self-test response levels. The internal self-test
(Phase 3) is exited and Phase 4 is entered upon completing
the second of any two successful self-test cycles.
A self-test cycle is considered failed if the change in the sensor
output value is not within the expected levels. The self-test cycle
is then repeated. The self-test cycle is run a maximum of six
times. The internal self-test (Phase 3) is exited and the error
state entered if fewer than two of the six self-test cycles pass.
Once the error state is entered, the self-test error code is
transmitted until the device is reset.
The internal self-test sequence is as follows:
1.
Wait 32 consecutive ADC samples.
2.
Average 64 consecutive ADC samples (V
STZ1
).
3.
Enable self-test voltage.
4.
Wait 32 consecutive ADC samples.
5.
Average 64 consecutive ADC samples (V
ST
P).
6.
Disable self-test voltage.
7.
Wait 32 consecutive ADC samples.
8.
Average 64 consecutive ADC samples (V
STZ2
).
9.
Compare measured values.
a.
Compare (V
STZ1
) to specified minimum and maximum
offset tolerance.
b.
Compare (V
STZ2
) to specified minimum and maximum
offset tolerance.
c.
Calculate difference (V
STP
) − (V
STZ1
) and compare to
specified minimum and maximum difference.
d.
Calculate the absolute difference (V
STZ1
) − (V
STZ2
) and
compare to the maximum value.
e.
If delta is less than or equal to four counts (10 bits),
then the self-test is a pass.
f.
If delta is greater than or equal to five counts (10 bits),
then the self-test is a fail.
10.
If any measurements in Step 9 fail to achieve the defined
limits, then repeat Step 1 through Step 9. Repeat a maximum
of five times.
11.
If fewer than two out of the six self-test cycles pass, an internal
self-test error flag is set. The error state is then entered. The
self-test error code is sent until the device is reset.
12.
Phase 4 is entered upon completing the second of any two
successful self-test cycles.
Influence of MD Selections On Transmitted Self-Test Data
Table 36. Phase 3 Data Transmitted During Internal Self-Test
MD1 MD0 Data
0 0 Device
OK
0 1 Range
1 0 Delimiter
1 1 Device
OK
When the internal self-test mode is selected, the type of data
transmitted during Phase 3 is dependent on the setting of the
Phase 2 mode select bits (MD1 and MD0). See Table 36 and
Table 39 for the
Device OK code. See the Phase 2: Device Data
Transmission section for specifics of the delimiter and range codes.
