17000048 - Monitor ADC Conversion Time Exceeds Specification:
DESCRIPTION:
The minimum conversion time of the Monitor ADC (ADC0) is 600 ns (instead of 500 ns as per the specifications). Therefore, the maximum
sampling rate of the ADC0 is 1.667 MSPS.
WORKAROUND:
None.
APPLIES TO REVISION(S):
0.0
17000049 - FOCP_LATCH_0/1/2 Latches Have Incorrect Power-Up Value:
DESCRIPTION:
During power-up, the status bits of the
FOCP_LATCH_0
,
FOCP_LATCH_1
, and
FOCP_LATCH_2
registers are set to 1.
WORKAROUND:
Reading the
FOCP_LATCH_0
,
FOCP_LATCH_1
, and
FOCP_LATCH_2
registers after power-up clears the latches and allows normal
operation. The ADCC software drivers include the
adi_adcc_GetRegister()
function to read the Analog Front End (AFE) registers
through the ADCC module. The ADCC drivers are available in the EVAL-CM41X-EZBRD/EZLITE evaluation platform Board Support Package
(BSP).
The following is an example to read from the
FOCP_LATCH_0, FOCP_LATCH_1, FOCP_LATCH_2
registers:
#include <drivers/adcc/adi_adcc.h>
ADI_ADCC_HANDLE handle;
ADI_ADCC_RESULT result;
uint32_t val;
static char space[ADI_ADCC_MEMORY];
result = adi_adcc_Open(0, space, &handle, false);
result = adi_adcc_GetRegister(handle, REG_USER_CONFIG_REG0_STATUSREG0, &val);
if (result == ADI_ADCC_SUCCESS)
{
/* Success! */
}
else
{
/* Failure! */
}
For more information about the APIs, refer to Device Driver documentation and example codes in the Board Support Package (BSP).
APPLIES TO REVISION(S):
0.0
17000050 - CRC On Over Voltage and Under Voltage DAC Are Incorrect:
DESCRIPTION:
The CRC values on the Over Voltage (OV) DAC and Under Voltage (UV) DAC are incorrect.
WORKAROUND:
Do not use CRC on the OV DAC or UV DAC.
APPLIES TO REVISION(S):
0.0
ADSP-CM411F/412F/413F/416F/417F/418F/419F
NR004483C | Page 6 of 12 | July 2017
Silicon Anomaly List
