17000067 - ADCC Frame Interrupt Status Register Must Be Cleared Between Frames:
DESCRIPTION:
When the
ADCC_NUMFRAMx
register is zero, the
ADCC_FISTAT.FINTx
bit is set after all the events related to a frame have completed.
When the
ADCC_NUMFRAMx
register is non-zero, the
ADCC_FISTAT.LFINTx
bit is also set after all the events related to all the frames
(
ADCC_NUMFRAMx
+ 1) have completed.
When the
ADCC_FISTATx
status bits are set, they must be cleared before the next ADCC timer trigger. Else, a trigger overrun error
interrupt (
ADCC_ERR
) is generated, which stops subsequent sampling, leading to data loss. An event interrupt handler
(
ADCC_TMR_EVT
) clears the
ADCC_FISTATx
status bits. This leads to a long sequence of actions (allowing the sampling to complete,
DMA to drain, and handler to be invoked), which may prevent three to five ADC conversion slots in the frame from being used, especially
at higher conversion rates.
WORKAROUND:
1. Use the
ADCC_TMRx_EVT
trigger master source to trigger a memory DMA transfer that writes to the ADCC system MMR space to
clear the
ADCC_FISTAT.FINTx
bits. This removes the core from processing the event and automates hardware handling for it.
2. Periodically update the
ADCC_NUMFRAMx
register to prevent the
ADCC_FISTAT.LFINTx
bit from getting set. The
ADCC_NUMFRCNT
register increments until it reaches the value in the
ADCC_NUMFRAMx
register, upon which the
ADCC_FISTAT.LFINTx
bit is set. Read the
ADCC_NUMFRCNT
register periodically, and update the
ADCC_NUMFRAMx
register to a
value that is less than the value read. For example, perform this check and adjustment in the ADCC timer event handler triggered by
assertion of the
ADCC_FISTAT.FINTx
bit. When the
ADCC_NUMFRAMx
register is non-zero, the delay incurred to clear the
ADCC_FISTAT.FINTx
bit will not cause an overflow error.
APPLIES TO REVISION(S):
0.0
17000075 - Primary ADC Conversions May Fail with Higher Delays Between Subsequent Conversions:
DESCRIPTION:
At room temperature, primary ADC (ADC1 and ADC2) conversion fails when the delay between the subsequent conversions is greater
than 2.8 ms.
This issue can occur with single-channel conversions or simultaneous conversions. In the case of simultaneous sampling conversions, only
the first conversion fails.
WORKAROUND:
The following workarounds can be used:
1. Place an additional NOP between the conversions.
2. Set the delay between the conversions to less than 2.8 ms on the primary ADCs.
APPLIES TO REVISION(S):
0.0
17000076 - First Conversion of ADC0 Fails after AFE Registers Are Accessed:
DESCRIPTION:
When a read/write operation is performed on the
AFE_STATUSREG0
,
AFE_STATUSREG1
, or
AFE_USERCFG
registers, the first
conversion on ADC0 fails. For example, the AFE Initialization after power-on-reset is done via the ADC0 interface (one time initialization). If
ADC0 is used in the application, the first conversion fails. This issue also occurs when FOCP status reading or DAC selection is performed,
followed by ADC0 conversion.
WORKAROUND:
Discard the first sample or perform a dummy access on ADC0.
APPLIES TO REVISION(S):
0.0
ADSP-CM411F/412F/413F/416F/417F/418F/419F
NR004483C | Page 11 of 12 | July 2017
Silicon Anomaly List
