17000064 - Back-to-back Writes to Internal SRAM May Be Lost:
DESCRIPTION:
When back-to-back writes are performed to the same 32 KB bank of the internal SRAM, the first write may be lost if address bit 14 is
different (all other bits are the same) on the second write.
The figure shows an example where address bit 14 is different for two accesses.
WORKAROUND:
The following workarounds utilize memory placement strategies, where two consecutive write addresses are not 16 KB apart.
For core-based accesses, the anomaly can occur on adjacent writes on the same bus between a local and global variable with addresses
16 KB apart and in the same bank.
In this case, the workaround is to use linker segments for code and variables to segregate them in a single 16 KB bank. If the total size is
greater than 16 KB, place the variables in a separate 32 KB bank.
For DMA-based accesses, there are several cases to consider:
1. If DMA requires less than 16 KB of data space or DMA requires between 16 KB and 32 KB of data space, but less than 16 KB for DMA
writes, the workaround is to place the segregated write buffers either at the top or bottom half of the 32 KB bank. Ensure that the
writable DMA data regions and read-only DMA data regions are in different half banks. Core-writable variables may be placed in the
other half of the 32 KB bank that contains read-only DMA regions.
The figure shows the memory placement when DMA and Core write buffers are less than 16 KB.
2. If DMA requires more than 16 KB but less than 32 KB for writes, and DMA writes are a single linear stream, the workaround is to place
the write data buffer in a single bank that has data in both halves of the bank. This issue does not exist in case of a linear addressed
DMA.
If DMA writes are not sequential and ordered and the DMA buffer requires more than 16 KB, the region must start from the higher
half of the bank and continue into the lower half of the next bank. Core-writable variables may be placed in the other half of the 32
KB bank that contains read-only DMA regions.
The figure shows the memory placement when DMA write buffers are between 16 KB and 32 KB.
ADSP-CM411F/412F/413F/416F/417F/418F/419F
NR004483C | Page 9 of 12 | July 2017
Silicon Anomaly List
