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SUMMARY OF SILICON ANOMALIES

The following table provides a summary of ADSP-CM411F/412F/413F/416F/417F/418F/419F anomalies and the applicable product
revision(s) for each anomaly.

No.

ID

Description

Rev

 0.0

Rev

 C

  1

17000033

SMC Byte Enable Signals Tri-State during Read Operations

x

.

  2

17000035

Timer0 Status Interrupt Is Not Functional

x

.

  3

17000036

JTAG May Inadvertently Enter EXTEST Mode

x

.

  4

17000038

M0 DMA Debug Halt Is Not Functional

x

.

  5

17000040

Internal LDO Increases VDD_INT

x

.

  6

17000041

Incorrect VMU Voltage Trip Values

x

.

  7

17000042

Oscillator Watch Dog Frequency Is Not Correct

x

.

  8

17000043

ADC Reference Voltages Do Not Match Specification

x

.

  9

17000044

DAC Output Current Limit Is Less Than Specified

x

.

 10

17000046

ADC Auxiliary Bypass Mode Cannot Be Cleared By Register Write

x

.

 11

17000048

Monitor ADC Conversion Time Exceeds Specification

x

.

 12

17000049

FOCP_LATCH_0/1/2 Latches Have Incorrect Power-Up Value

x

.

 13

17000050

CRC On Over Voltage and Under Voltage DAC Are Incorrect

x

.

 14

17000055

Flash Security Features Are Not Fully Operational

x

.

 15

17000057

PLL Malfunctions at Higher Frequencies

x

.

 16

17000059

Security Keys for Devices Connected in a JTAG Chain Require Leading Zeroes

x

.

 17

17000060

adi_rom_MemCopy() ROM API Leaves MDMA Enabled

x

.

 18

17000063

System Watchpoint Units 3 and 4 Incorrectly Alias Master IDs

x

.

 19

17000064

Back-to-back Writes to Internal SRAM May Be Lost

x

.

 20

17000066

Manual ECC Error Diagnostic Testing of Flash Memory Is Not Functional

x

.

 21

17000067

ADCC Frame Interrupt Status Register Must Be Cleared Between Frames

x

.

 22

17000075

Primary ADC Conversions May Fail with Higher Delays Between Subsequent Conversions

x

.

 23

17000076

First Conversion of ADC0 Fails after AFE Registers Are Accessed

x

.

 24

17000077

FOCP Over Voltage and Under Voltage DAC Output Limited by Offset and Gain Errors

x

.

 25

17000080

Logic Block Array (LBA) Combinatorial Mode Is Not Functional

x

.

 26

17000082

Primary ADC Gain Error Correction Is Not Functional

.

x

 27

17000083

Floating Point Saturation Unit Is Not Functional

x

.

Key: x = anomaly exists in revision
          . = Not applicable

ADSP-CM411F/412F/413F/416F/417F/418F/419F

NR004483C   |   Page 2 of 12   |   July 2017

 

 

Silicon Anomaly List

Содержание ADSP-CM411F

Страница 1: ...ons and Changes 07 24 2017 C PrB Added Silicon Revision C Added Anomalies 17000067 17000080 17000082 17000083 06 27 2016 B PrB Added Anomalies 17000063 17000064 17000066 17000075 17000076 17000077 Rev...

Страница 2: ...t x 14 17000055 Flash Security Features Are Not Fully Operational x 15 17000057 PLL Malfunctions at Higher Frequencies x 16 17000059 Security Keys for Devices Connected in a JTAG Chain Require Leading...

Страница 3: ...s the SMC0_AOE signal is high during write operations APPLIES TO REVISION S 0 0 2 17000035 Timer0 Status Interrupt Is Not Functional DESCRIPTION SYSBLK_SISTAT15 TIMER0_STAT bit is always read as 0 The...

Страница 4: ...bit of the voltage trim values for the VDD_EXT and VDD_INT power supply trip levels are not programmed at power on reset As a result of this 1 The VMU may detect a fault when the VDD_EXT and VDD_INT...

Страница 5: ...erted to non bypass mode WORKAROUND If the auxiliary bypass bit is set a soft reset is required to take the AFE out of auxiliary buffer bypass mode The ADCC drivers include the adi_adcc_SetRegister fu...

Страница 6: ...s are available in the EVAL CM41X EZBRD EZLITE evaluation platform Board Support Package BSP The following is an example to read from the FOCP_LATCH_0 FOCP_LATCH_1 FOCP_LATCH_2 registers include drive...

Страница 7: ...er debug security bits For all other parts zeroes are appended with respect to the position of the part in the scan chain This issue occurs when security keys are provided through the TAPC security sc...

Страница 8: ...T2_TX 00000X011 DMA7 SPI1_RX UART2_RX 00000X100 DMA8 HAE_IN0 UART3_TX 00000X101 DMA9 HAE_OUT UART3_RX 00000X110 DMA10 HAE_IN1 UART4_TX SPORT0A 00000X111 DMA11 SPORT0B UART4_RX 01000X000 DMA12 MDMA0_RD...

Страница 9: ...t less than 16 KB for DMA writes the workaround is to place the segregated write buffers either at the top or bottom half of the 32 KB bank Ensure that the writable DMA data regions and read only DMA...

Страница 10: ...sed accesses a high DMA latency value M4P_SRAM_CFG_DMAMAXLAT decreases the probability of writes getting lost when back to back writes are performed to SRAM APPLIES TO REVISION S 0 0 20 17000066 Manua...

Страница 11: ...ADCC_NUMFRAMx register to a value that is less than the value read For example perform this check and adjustment in the ADCC timer event handler triggered by assertion of the ADCC_FISTAT FINTx bit Whe...

Страница 12: ...ROUND None APPLIES TO REVISION S 0 0 26 17000082 Primary ADC Gain Error Correction Is Not Functional DESCRIPTION Primary ADC ADC1 and ADC2 gain error correction is not functional This feature is disab...

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