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DETAILED LIST OF SILICON ANOMALIES

The following list details all known silicon anomalies for the ADSP-CM411F/412F/413F/416F/417F/418F/419F including a description,
workaround, and identification of applicable product revisions.

1.

  17000033 - SMC Byte Enable Signals Tri-State during Read Operations:

DESCRIPTION:

During SMC read operations, the byte enable signals (

SMC0_ABE0

 and 

SMC0_ABE1

) are tri-stated instead of being driven low. Therefore,

when an 8-bit SMC write access is followed by a 16-bit or 32-bit read access, the read access may fail if the device requires active low byte
enable signals during read operations.

WORKAROUND:

While interfacing with the external SRAM, the SRAM byte enable signals can be driven low during read operations using external logic as
shown in the figure.

For SMC read operations, the 

SMC0_AOE

 signal is low. This drives the 

SRAM_BHE

 and 

SRAM_BLE

 signals low.

This external logic does not affect the SMC write operations, as the 

SMC0_AOE

 signal is high during write operations.

APPLIES TO REVISION(S):

0.0

2.

  17000035 - Timer0 Status Interrupt Is Not Functional:

DESCRIPTION:

SYSBLK_SISTAT15.TIMER0_STAT

 bit is always read as 0. Therefore, Timer0 Status Interrupt is not functional.

WORKAROUND:

None.

APPLIES TO REVISION(S):

0.0

3.

  17000036 - JTAG May Inadvertently Enter EXTEST Mode:

DESCRIPTION:

When performing a JTAG instruction register scan in multiple parts using the Pause-IR JTAG state, the JTAG controller erroneously enters
the EXTEST state while in the Pause-IR state. The I/O pins may incorrectly drive the rest of the system for multiple JTAG cycles.

WORKAROUND:

Using Pause-IR to break the instruction scan into parts must be avoided. If Pause-IR is used, ensure the ADI JTAG Instruction Register does
not have a value of b'00000 at the pause point. When in the Exit-IR state, if the ADI JTAG Instruction Register contains a value of b'00000,
the JTAG clock must not be stopped. This leaves the I/O pins in an undetermined state until the JTAG clocks resume.

APPLIES TO REVISION(S):

0.0

ADSP-CM411F/412F/413F/416F/417F/418F/419F

NR004483C   |   Page 3 of 12   |   July 2017

 

 

Silicon Anomaly List

Содержание ADSP-CM411F

Страница 1: ...ons and Changes 07 24 2017 C PrB Added Silicon Revision C Added Anomalies 17000067 17000080 17000082 17000083 06 27 2016 B PrB Added Anomalies 17000063 17000064 17000066 17000075 17000076 17000077 Rev...

Страница 2: ...t x 14 17000055 Flash Security Features Are Not Fully Operational x 15 17000057 PLL Malfunctions at Higher Frequencies x 16 17000059 Security Keys for Devices Connected in a JTAG Chain Require Leading...

Страница 3: ...s the SMC0_AOE signal is high during write operations APPLIES TO REVISION S 0 0 2 17000035 Timer0 Status Interrupt Is Not Functional DESCRIPTION SYSBLK_SISTAT15 TIMER0_STAT bit is always read as 0 The...

Страница 4: ...bit of the voltage trim values for the VDD_EXT and VDD_INT power supply trip levels are not programmed at power on reset As a result of this 1 The VMU may detect a fault when the VDD_EXT and VDD_INT...

Страница 5: ...erted to non bypass mode WORKAROUND If the auxiliary bypass bit is set a soft reset is required to take the AFE out of auxiliary buffer bypass mode The ADCC drivers include the adi_adcc_SetRegister fu...

Страница 6: ...s are available in the EVAL CM41X EZBRD EZLITE evaluation platform Board Support Package BSP The following is an example to read from the FOCP_LATCH_0 FOCP_LATCH_1 FOCP_LATCH_2 registers include drive...

Страница 7: ...er debug security bits For all other parts zeroes are appended with respect to the position of the part in the scan chain This issue occurs when security keys are provided through the TAPC security sc...

Страница 8: ...T2_TX 00000X011 DMA7 SPI1_RX UART2_RX 00000X100 DMA8 HAE_IN0 UART3_TX 00000X101 DMA9 HAE_OUT UART3_RX 00000X110 DMA10 HAE_IN1 UART4_TX SPORT0A 00000X111 DMA11 SPORT0B UART4_RX 01000X000 DMA12 MDMA0_RD...

Страница 9: ...t less than 16 KB for DMA writes the workaround is to place the segregated write buffers either at the top or bottom half of the 32 KB bank Ensure that the writable DMA data regions and read only DMA...

Страница 10: ...sed accesses a high DMA latency value M4P_SRAM_CFG_DMAMAXLAT decreases the probability of writes getting lost when back to back writes are performed to SRAM APPLIES TO REVISION S 0 0 20 17000066 Manua...

Страница 11: ...ADCC_NUMFRAMx register to a value that is less than the value read For example perform this check and adjustment in the ADCC timer event handler triggered by assertion of the ADCC_FISTAT FINTx bit Whe...

Страница 12: ...ROUND None APPLIES TO REVISION S 0 0 26 17000082 Primary ADC Gain Error Correction Is Not Functional DESCRIPTION Primary ADC ADC1 and ADC2 gain error correction is not functional This feature is disab...

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