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FIREFINDER SERIES II
INSTALLATION,
COMMISSIONING
&
OPERATION
4.17 Addressable Loop Termination Board (BRD86DLTB-B)
The Addressable Loop Termination Board acts as the interface between the external addressable
devices and the control and monitoring functions of the
FireFinder
. Each board provides
terminations for two loops. One slave CPU is required per loop.
Note:
Apollo devices L2 is +ve (positive), L1 is -ve (negative)
Connect the XP-95 / DISCOVERY loop to the panel as shown below.
AMPAC strongly recommend that the
LoopManager
test set is used to check that the Apollo loop
has been correctly installed and commissioned before connecting it to the
FireFinder
™.
Loop Parameters
126 Apollo Devices (i.e. maximum address range)
500mA Current Max
S/C protection circuitry activates at approximately 650mA
Maximum length 1.2km
Note:
To achieve full current, the Loop Trip current in Loop Parameters needs to be set to
300mA (
ConfigManager
)
CONNECTIONS
CN1 / 2
To 302-699
CN3 / 4
27VDC in / out
TB1 / 2
To Addressable loop devices
REGULATED
27VDC In / Out
T0 SLAVE CPU
CN1
LOOP NORMAL
LED OUT
monitoring
each Loop is ON
LED OUT & IN ON
indicates a fault
on the Loop
( S/C, O/C ) and
the Loop is being
monitored in
both directions
LOOP IN FAULT
R +
L1
L2
-R
L1
L2
-R
L1
L2
-R
R +
R +
Wiring Shown
Above is for a
XP95 Circuit
with one Detector
Having LED
Monitoring
L1
L1
L1
L2
L2
L2
IN
OUT
IN
OUT
BRD86DLTB2-
LOOP 2
LOOP 1
+
-
-
+
+
-
IN
OUT
-
+
+
-
D C
+
-
D C
OUT
IN
L
O
O
P
1
C
O
N
T
R
O
L
L
O
O
P
2
C
O
N
T
R
O
L
-5V
+5V
+12V
+40V
0V
LOOP 1 RETURN SENSE
LOOP 2 RETURN SENSE
TRI WAVE
POWER
LOOP1
OUT
I N
LOOP1
OUT
LOOP2
I N
LOOP2
C52
C
5
0
R100
R92
R76
R67
R43
R34
R23
R12
R
1
3
8
R148
R142
R
1
3
5
R146
R140
R
5
1
R
8
1
R
5
0
R
1
0
4
R103
R
1
0
8
R
1
0
6
R5
R
5
6
R55
R54
R52
Q26
Q10
Q17
Q
1
5
Q18
Q13
Q11
Q2
Q8
Q6
Q9
Q4
Q1
D12
D13
D6
D5
C17
C41
C97
N1236
R
8
4
R
1
0
5
R4
R127
R
1
2
5
R155
R
1
3
7
R
1
2
3
R
1
5
9
R149
R
1
5
1
R
1
6
0
R
1
6
6
R
1
6
5
R
1
6
4
Q
1
9
Q23
Q21
D19
D15
C
6
5
C49
C
7
6
C54
C
6
1
C
8
7
C77
C82
C75
C
9
0
C
8
9
C100
C94
U1
U8
U21
U22
R
1
8
4
R
1
7
9
R
1
7
8
R
1
7
5
R
1
7
3
R174
R
1
7
7
R176
C96
C109
C
1
0
8
C
1
0
2
C106
C
1
0
1
C95
U
2
3
ZD23
ZD17
ZD21
ZD22
ZD20
ZD13
ZD16
Z
D
1
8
ZD15
Z
D
1
4
ZD12
ZD6
ZD10
Z
D
1
1
ZD9
ZD2
ZD4
Z
D
7
ZD5
U9
U7
U12
U10
U5
U14
U16
U20
U3
U2
U
1
9
U6
U4
U13
U15
U18
U
1
7
U24
U25
TH2
TH1
TH3
TB2
TB1
RN1
R139
R
6
2
R
6
3
R
7
1
R
8
5
R
5
7
R
8
3
R119
R
6
1
R
8
6
R
1
1
3
R
8
7
R93
R
8
9
R114
R
1
2
2
R
7
7
R
1
2
1
R
1
2
0
R
1
3
4
R
6
6
R64
R
9
7
R143
R
1
5
8
R
1
6
8
R110
R
1
6
7
R147
R136
R2
R3
R9
R
3
7
R
3
0
R
1
1
1
R
3
8
R115
R
3
9
R
4
0
R
1
1
8
R112
R20
R
1
1
6
R
1
1
7
R131
R
1
3
3
R44
R141
R157
R
1
6
3
R109
R
1
6
2
R145
R181
R180
R
1
8
2
R
1
8
3
Q16
Q28
Q7
Q27
L4
L3
L6
L8
L2
L1
L5
L7
L9
D
1
4
D17
D7
D1
D16
D22
D21
CN3
CN4
CN2
CN1
C
2
6
C46
C2
C21
C70
C
3
1
C
3
9
C48
C38
C45
C35
C58
C
4
0
C64
C
6
8
C
3
6
C
2
7
C73
C74
C
8
6
C83
C56
C69
C
1
5
C6
C
1
6
C24
C57
C63
C
6
7
C3
C71
C72
C85
C81
C55
C103
C104
C105
C99
C107
C59
C
9
1
C
9
2
C78
C84
C80
C
8
8
C
6
2
C53
C
7
9
C51
C
6
6
C60
D18
D20
Q22
Q24
Q
2
0
R
1
7
0
R
1
7
1
R
1
7
2
R
1
6
1
R
1
5
2
R
1
5
0
R
1
6
9
R
1
2
4
R
1
4
4
R156
R
1
2
8
R130
U26
HSNK1
C1
C98
ZD1
R
1
4
R132
RN2
Q25
C34
+
-
+
-
-
-
T0 SLAVE CPU
CN1
Figure 26: Addressable Loop Termination Board