Table 7: MIO Peripheral Mapping (cont'd)
MIO[0:25] Bank 500
MIO[26:51] Bank 501
MIO[52:77] Bank 502
7
QSPI_UPR
33
PMU GPO
59
USB0
8
QSPI_UPR
34
PMU GPO
60
USB0
9
QSPI_UPR
35
PMU GPO
61
USB0
10
QSPI_UPR
36
PMU GPO
62
USB0
11
QSPI_UPR
37
PMU GPO
63
USB0
12
QSPI_UPR
38
GPIO
64
GEM3
13
GPIO
39
SD1
65
GEM3
14
I2C0
40
SD1
66
GEM3
15
I2C0
41
SD1
67
GEM3
16
I2C1
42
SD1
68
GEM3
17
I2C1
43
SD1
69
GEM3
18
UART0
44
Not assigned/no connect
70
GEM3
19
UART0
45
SD1
71
GEM3
20
Not assigned/no connect
46
SD1
72
GEM3
21
Not assigned/no connect
47
SD1
73
GEM3
22
GPIO
48
SD1
74
GEM3
23
GPIO
49
SD1
75
GEM3
24
Not assigned/no connect
50
SD1
76
GEM3
25
Not assigned/no connect
51
SD1
77
GEM3
Quad-SPI Flash Memory (MIO 0–12)
, callout 5]
The Micron dual MT25QU02GCBB8E12-0SIT serial NOR flash Quad-SPI memories are capable
of holding the boot image for the Zynq Ult RFSoC. This interface is used to support
QSPI32 boot mode as defined in the Zynq Ult Device Technical Reference Manual
(
The dual Quad-SPI flash memory located at U11/U12 provides 4 Gb of non-volatile storage that
can be used for configuration and data storage.
• Part number: MT25QU02GCBB8E12-0SIT (Micron)
• Description:
○
2 Gb/256 MB
○
2.7V – 3.6V 24-ball TBGA
○
90 MHz DTR/133 MHz STR
• Datapath width: 8 bits
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
27