Table 18: Clock Connections to ZU67DR U1 (cont'd)
Clock Source Ref. Des. and
Pin
Net Name
I/O Standard
U43.38
SI5381_GTR_REF_CLK_P
U43.37
SI5381_GTR_REF_CLK_N
U43.42
SI5381_PL_CLK_P
LVDS
U43.41
SI5381_PL_CLK_N
LVDS
U43.45
SI5381_GTR_REFCLK_USB3_P
U43.44
SI5381_GTR_REFCLK_USB3_N
U43.51
SI5381_CLK_125_P
LVDS
U43.50
SI5381_CLK_125_N
LVDS
U43.54
SI5381_SMA_SE (undefined on schematic)
LVCMOS
ADC_CLK_226
J8 (P) SMA CONN.
ADC_CLK_226_P
See Zynq Ult RFSoC Data Sheet:
DC and AC Switching Characteristics
J98 (N) SMA CONN.
ADC_CLK_226_N
See Zynq Ult RFSoC Data Sheet:
DC and AC Switching Characteristics
DAC_CLK_228
J99 (P) SMA CONN.
DAC_CLK_228_P
See Zynq Ult RFSoC Data Sheet:
DC and AC Switching Characteristics
J100 (N) SMA CONN.
DAC_CLK_228_N
See Zynq Ult RFSoC Data Sheet:
DC and AC Switching Characteristics
U409 8A34001 eCPRI Clock
U409.A9 (Q1)
8A34001_Q1_OUT_P
U409.B9 (Q1)
8A34001_Q1_OUT_N
U409.A11 (Q2)
8A34001_Q2_OUT_P
LVDS
U409.B11 (Q2)
8A34001_Q2_OUT_N
LVDS
U409.A12 (Q3)
8A34001_Q3_OUT_P
LVDS
U409.B12 (Q3)
8A34001_Q3_OUT_N
LVDS
U409.M8 (Q7)
8A34001_Q7_OUT_P
U409.L8 (Q7)
8A34001_Q7_OUT_N
U409.A6 (Q8)
8A34001_Q8_OUT_P
LVDS
U409.B6 (Q8)
8A34001_Q8_OUT_N
LVDS
U409.M6 (Q11)
8A34001_Q11_OUT_P
U409.L6 (Q11)
8A34001_Q11_OUT_N
Notes:
1.
U1 ZU67DR Bank 503 supports LVCMOS18 level inputs.
2.
Series capacitor coupled, U1 MGT (I/O standards do not apply).
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
44