PMU GPO (MIO 32-37)
The platform management unit (PMU) within the Zynq Ult RFSoC signals power domain
changes using the PMU output pins for deep-sleep mode. The Zynq Ult RFSoC PMU
GPO pins are connected to inputs of the MSP430 system controller through the TXS0108E level-
shifter U37. The RFSoC U1 Bank 501 and MSP430 U38 pin numbers are listed in the following
table.
Table 14: XCZU67DR to MSP430 Connections
Net Name
MSP430 U38
Pin Name
MIO37_PMU_GPO5
P1_0
MIO36_PMU_GPO4
P1_1
MIO35_PMU_GPO3
P1_2
MIO34_PMU_GPO2
P1_3
MIO33_PMU_GPO1
P1_4
MIO32_PMU_GPO0
P1_5
Through the I2C0 bus U1 PS-side MIO[14:15] pins, the PMU has access to the board power
controller PMBus bus (IRPS5401_SDA/SCL) and power monitor PMbus ( INA226_PMBUS_SDA/
SCL). See
for additional details.
See the Zynq Ult Device Technical Reference Manual (
) for details about the PMU
interface.
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU670 board XDC file, referenced in
Appendix B: Xilinx Design Constraints
SDIO (MIO 39-51)
A PS-side interface to an SD card connector is provided for booting and file system storage. This
interface is used for the SD boot mode and supports SD3.0 access post boot.
SD Card Interface
, callout 7]
The ZCU670 board includes a secure digital input/output (SDIO) interface to provide access to
general purpose non-volatile SDIO memory cards and peripherals. Information for the SD I/O
card specification can be found on the
websites. The
ZCU670 SD card interface supports the SD1_LS configuration boot mode documented in the
Zynq Ult Device Technical Reference Manual (
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022
ZCU670 Board User Guide
35