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Background
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
© November 2008
Altera Corporation
Single-ended or Differential DQS Signaling
Stratix III devices directly support differential DQS mode and the single-ended
standard supported in previous device families. DDR3 SDRAM mandates differential
DQS signaling.
Differential DQS strobe operation enables improved system timing due to reduced
crosstalk and simultaneous switching noise on the strobe output drivers.
DDR Registers
Similar to the previous generation of devices, DDR registers are provided on all sides
of the device so that DDR I/O structures can be directly implemented in the IOE, thus
saving core logic and ensuring tight skew is easily maintained, which eases timing.
Stratix III devices now feature four DLLs, so DQS capture mode is now supported on
every side of the device.
Alignment and Synchronization Registers
In previous device families the resynchronization registers had to be located in the
core of the device, which made the placement of these registers with respect to the
DDR IOE critical to ensure that timing is achieved. Stratix III devices have been
enhanced to include the alignment and synchronization registers directly within the
IOE, hence timing is now significantly improved and you are no longer concerned
with ensuring critical register placement with respect to the DDR IOE. Typically, the
resynchronization register is clocked via a dedicated output from the PLL. However,
it may also be clocked directly from the read-leveling delay chain. The output
alignment registers are typically clocked from the PLL.
1
Generally alignment and synchronization registers are optional and can be bypassed
if not required; for ALTMEMPHY-based designs, these registers are required.
Regardless of interface speed, ALTMEMPHY always implements synchronization
registers. Hence latency through the PHY may not be optimal for lower frequency
designs.
Stratix III devices include only one leveling delay chain per I/O subbank. For
example, subbank 1A includes a single leveling chain, 1B includes a second leveling
chain, and so on.
If the half-rate resynchronization clock is sourced from the leveling delay chain, it
may be cascaded from bank to bank, say 1A to 1B. In this configuration memory
controllers must form a single contiguous block of DQS groups that are not staggered
or interleaved with another memory controller. Additionally two PHYs cannot share
the same sub-bank as only one leveling delay chain exists per sub-bank.
Half Data Rate Registers
As external memory interface clock speeds increase, the core f
MAX
can become the
limiting factor in interface design. A common solution, which increases core f
MAX
timing problems, is to implement a half data rate architecture. This solution has the
effect of doubling the data width on the core side interfaces compared to a full-rate
SDR solution, but also halves the required operating frequency. To simplify PHY
design and provide easier design constraints, Stratix III devices include dedicated
full-rate to half-rate registers within the IOE.
