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Background
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
© November 2008
Altera Corporation
Address and Command Signals
Address and command signals in DDR3 SDRAM devices are clocked into the memory
device using the
CK
or
CK#
signal. These pins operate at single data rate (SDR) using
only one clock edge. The number of address pins depends on the DDR3 SDRAM
device capacity. The address pins are multiplexed, so two clock cycles are required to
send the row, column, and bank address. The
CS
,
RAS
,
CAS
,
WE
,
CKE
, and
ODT
pins are
DDR3 SDRAM command and control pins.
The DDR3 SDRAM address and command inputs do not have a symmetrical setup
and hold time requirement with respect to the DDR3 SDRAM clocks,
CK
, and
CK#
.
For SDRAM high-performance controllers in Stratix III devices, the address and
command clock is always one of the PLL dedicated clock outputs whose phase can be
adjusted to meet the setup and hold requirements of the memory clock. The address
and command clock is also typically half-rate, although a full-rate implementation
can also be created. The command and address pins use the DDIO output circuitry to
launch commands from either the rising or falling edges of the clock. The chip select
(
CS_N
) clock enable (
CKE
) and
ODT
pins are only enabled for one memory clock cycle
and can be launched from either the rising or falling edge of the address and
command clock signal. The address and other command pins are enabled for two
memory clock cycles and can also be launched from either the rising or falling edge of
the address and command clock signal.
1
In ALTMEMPHY-based solutions, the address and command clock
ac_clk_1x
is
always half rate. However, because of the output enable assertion,
CS_N
,
CKE
and
ODT
behave like full-rate signals even in a half-rate PHY.
PLL and DLL Features and Availability
Stratix III devices are well equipped to address the clocking requirements of external
DDR3 SDRAM interfaces. Stratix III PLLs have an increased number of outputs and
global clock routing resources when compared to earlier device generations. Stratix III
top and bottom PLLs feature 10 output (C) counters, also left and right PLLs feature 7
output (C) counters. This increased number of PLL outputs allows for the use of
dedicated clock phases.
In general, each Stratix III PLL has access to 4 global clocks (GCLK) and 6 regional
clocks (RCLK) (left and right) or 10 RCLK (top and bottom).
Stratix III devices also feature four DLLs (one located in each corner of the device).
The FPGA can support a maximum of four unique frequencies, with each DLL
running at one frequency. Each DLL can also support two different phase offsets,
which allow a single Stratix III device to support eight different DLL phase shift
settings. Additionally, each DLL can access the two sides adjacent to its location. Thus
each I/O bank is accessible by two different DLLs, giving more flexibility when
creating multiple frequency and phase-shift memory interfaces.
f
For more information, refer to the
Clock Networks and PLLs in Stratix III Devices
chapter
and the
Stratix III Device Handbook
.
shows PLL and DLL locations in Stratix III devices with global and regional
clock resources.
