Alpha Data ADM-XRC-II Pro, Руководство по оборудованию

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ADM- XP User Manual
ADM-XR-IIPro User Manual
Page 11 of 29 Version 0.2
within the V2Pro device and the allocation of the MGT resources on the board the MGT’s are currently limited
to 2.5GBps operation using the REFCLK input to the transceivers.
The MCLK signal is input to the FPGA to provide a user clock of between 10 and 200MHz, single ended. The
local bus uses LCLK to synchronize transfers between the bridge and the target and is derived from MCLK by
a divide by 2 in the ICS307. Although the clocks are related, phase is not guaranteed.
A summary of the clock pins is shown in the table below.
Bank VCCO GCLK Pin Signal Description
0 JP1 select 7P K22 IO_74N_0/GCLK7P
0 JP1 select 6S J22 IO_74P_0/GCLK6S
0 JP1 select 5P F22 IO_75N_0/GCLK5P
0 JP1 select 4S G22 IO_75P_0/GCLK4S
1 JP1 select 0S K21 IO_74P_1/GCLK0S
1 JP1 select 1P J21 IO_74N_1/GCLK1P
1 JP1 select 2S F21 IO_75P_1/GCLK2S
1 JP1 select 3P G21 IO_75N_1/GCLK3P
User clocks to / from XRM
4 2.5V 0P AT21 LCLK Local Bus Clock :-
MCLK divided by 2
4 2.5V 1S AU21 MCLK User programmable up to
200MHz. Default is 66MHz
4 2.5V 2P AP21 DDR2_clk Clock feedback DDR DRAM 1
4 2.5V 3S AN21 DDR1_clk Clock feedback DDR DRAM 0
2 2.5V - AB12 DDR1_clk
2 2.5V - AA12 DDR1_clkb
2 2.5V - AA10 DDR2_clk
2 2.5V - AA9 DDR2_clkb
Used for clock forwarding of
DDR clock outputs
5 2.5V 6P AU22 MGT_clk
5 2.5V 7S AT22 MGT_clkb
Clock for the MGTs
5 2.5V 4P AN22 PN4 fpga_P3
5 2.5V 5S AP22 PN4 fpga_N3
PN4 IO clocks
If required, XRM related clocks should be terminated on the XRM itself. No terminations are provided on the
XP main board.