Allen-Bradley 1395, Руководство по устранению неисправностей

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Malfunctions with Indications 2-3
A Soft Fault response will occur if the corresponding bit is set to 1. A
Warning response will occur if the corresponding bit is set to 0.
The default for all bits of parameter 623, when the parameter table is
initialized, is 1. This causes all of the faults listed in
Table 2.A to respond as
a Soft Fault type. For a fault to respond as a Warning Fault, the
corresponding bit must be set to 0 by the user. If the faults above are
configured as Warning Faults, then a provision should be made to report
these warnings through the PLC or other external device.
Configuring “Waiting Safe Arm Volts” (bit 5=0) and “Waiting Zero Arm
Current” (bit 6=0) as Warning faults is recommended. This allows the
current loop to attempt to correct the condition without causing nuisance
trips. Drive operation is continued even when these faults are configured as
Warning Faults. ALL other bits should be set to 1 in most applications.
Three warning faults can be disabled by bit manipulation of parameter 632:
If a bit is set to 1, that particular fault will not be reported in the fault
word (parameter 100).
Table 2.A Fault Select Parameter 623
Parameter 632 Associated Fault
Bit 0 = Motor Overload Pending VP-16, (reference parameter 720)
Bit 1 = Excessive armature volts demand VP-36
Bit 2 = Bridge Overload Pending VP-39 (reference parameter 615)
Bit
Fault
Number Fault Definition
Fault Description
0 VP-14 SCR Overtemp Occurs when the SCR heat sink (HST) thermo switch reaches 85 degrees C (185
degrees F) for 1 second. If bit 0 = 1, then a fault occurrence will cause a controlled
motor stop.
1 VP-15 Motor Overtemp Occurs when the external overtemp discrete input is low for specified delay of
Param 725. If bit 1 = 1, then a fault occurrence will cause a controlled motor stop.
2 VP-17 Overload Tripped Occurs when the armature current output has exceeded the selected motor
overload coefficients. These coefficients are selected in parameter 629 “Mtr
Overload Sel”. If bit 2 = 1, then a fault occurrence will cause a controlled motor stop.
3 VP-18 Stall Occurs when the armature current output is at current limit and velocity is within the
zero speed tolerance (parameter 710) for the time specified in parameter 727 “Stall
Delay”. If Bit 3 = 1, then a fault occurrence will cause a Coast Stop.
4 VP-20 AC Voltage Occurs when the incoming AC line voltage e15% or–20% of voltage
specified in parameter 617 “Rated AC Line” for 1 second. If Bit 4 = 1 then a fault
occurrence will cause a controlled motor stop.
5 VP-34 Waiting Safe
Arm Voltage Occurs when armature CEMF is too high to allow successful commutation during a
forward to reverse bridge change. If bit 5 =1, then a fault occurrence will cause a
Coast Stop. If bit 5 = 0, then an occurrence will cause the motoring bridge to be
held off, allowing the motor to coast to a lower CEMF. When an acceptable level is
reached the drive will allow a bridge change and operation will continue.
6 VP-35 Waiting Zero
Arm Current Occurs when the armature current does not go to zero when a bridge change is
commanded. If bit 6 = 1, then a fault occurrence will cause a Coast Stop. If bit 6 = 0,
then an occurrence will cause the drive to attempt to force the current to zero.
7 VP-31 Arm Bridge
Overload Trip Occurs when armature current output exceeds the predetermined armature bridge
overload coefficients which are based on 150% for 60 seconds, 200% for 10
seconds, 260% for 5 seconds. If bit 7 = 1, then a fault occurrence will cause a Coast
Stop.
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