[AK4675]
MS0963-E-00
2008/05
- 53 -
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits (
).
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0 0 0
Don’t care
Don’t care
8kHz
≤
fs
≤
12kHz
1 0 1
Don’t care
Don’t care
12kHz < fs
≤
24kHz
2 1
Don’t care
Don’t care
Don’t care
24kHz < fs
≤
48kHz
(default)
Others Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
ミ
PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, the LRCK and BICK pins go to “L” and irregular frequency clock is output from the MCKO pins at MCKO
bit is “1” before the PLL goes to lock state after PMPLL bit = “0”
å
“1”. If MCKO bit is “0”, the MCKO pin goes to “L”.
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, the BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
MCKO bit = “0”
MCKO bit = “1”
BICK pin
LRCK pin
After that PMPLL bit “0”
å
“1”
“L” Output
Invalid
“L” Output
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
Invalid
PLL Lock
“L” Output
See
1fs
Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
å
“1”. After that, the clock selected by
is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACR,
DACH and DACS bits.
MCKO pin
PLL State
MCKO bit = “0”
MCKO bit = “1”
After that PMPLL bit “0”
å
“1”
“L” Output
Invalid
PLL Unlock
“L” Output
Invalid
PLL Lock
“L” Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)