Agilent Technologies 16900A, Руководство по обслуживанию

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126 16900A, 16902A, and 16903A Service Guide
8
Theory of Operation
an on board EPROM at power up. The EPROM contents can
be changed (updated) through the system software via a
JTAG port.
A major function of this FPGA component is system
correlation; time alignment of the three modules and
possible other modules connected through the multiframe
port or trigger in connector. This is done with eight 52- bit
counters running at 1.6 GHz allowing relative time alignment
of eight seperate events. A 100 MHz clock is also selected
from three possible sources (internal, multiframe, external)
and a synchronizing signal is generated for time alignment
across multiframe.
A second major function of the FPGA is the logical
combination and routing of the module arm and trigger
lines: ARM, TRIG, FLAG. These signals are used by the
modules to start and stop each other in addition to
supplying the signals for real- time correlation.
The other FPGA functions include a system interface to
control the trigger input and output ports, target control
port, a serial DAC programmer and UARTs for multiframe.
PLD
The PLD is the low level system control element powered
from the AUX +5 V rail and continuously ON. It logically
controls the soft power ON/OFF through signal lines to the
CPU and and power switch monitoring. It physically turns
power ON/OFF via power on/off signals on the power supply
sense cables. In addition to the power switch starting a
power down sequence, two additional monitoring circuits
(overtemp and voltage rail) may cause the PLD to initiate
power down. Both of these conditions are "latched" faults
and require removing the power cord for 15 seconds to clear
the condition.
Voltage rail monitor
All six voltage rails are continuously monitored for an under
voltage fault condition. This could be caused by such things
as a failed power supply or a short circuit within the
instrument. When detected, both power supplies are
immediately shut down. At power up, there is a one second
time delay to allow the power to stabalize before the
monitoring circuit is enabled.