Agilent Technologies 16900A, Руководство по обслуживанию

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Theory of Operation
8
16900A, 16902A, and 16903A Service Guide 113
A second major function of the FPGA is the logical
combination and routing of the module arm and trigger
lines: ARM, TRIG, FLAG. These signals are used by the
modules to start and stop each other in addition to
supplying the signals for real time correlation.
The other FPGA functions include a system interface to
control the input and output ports, a serial DAC
programmer, and UARTs for multiframe.
Multiframe input/output
Multiframe is a proprietary bus used to connect multiple
16900A/16902A frames. It physically consists of two
connectors (input, output) which cable frames together in a
daisy chain configuration. It logically allows two or more
frames to appear and operate as one large frame. A LAN
connection between frames is used in addition to the
multiframe cable for fast data transfer.
The bus is physically 18 LVDS differential pairs plus ground.
The signals are 100 MHz clock, SYNC, START, eight flags,
RUN, UARTS (receive and transmit), and "cable on"
detection. They route from FPGA to FPGA across frames
with no other hardware other than termination resistors.
The UARTS allow frames to communicate at a low level to
identify themselves and pass IP addressing information. The
"cable on" detection lets the system know when a frame has
been added or removed via power up/down or cable changes.
Together, these functions allow a multiframe setup to
completely self- configure itself and appear as one integrated
measurement system.
Target control port
The target control port consists of eight bi- directional LVTTL
lines driven from the FPGA through 51
Ω
series dampening
resistors. These lines are configured by the user as either
READ or WRITE lines and are used for basic system
monitoring and control. For example when driving a target
system reset line or monitoring system power on.
Trigger IN/OUT
These two BNCs function as an external trigger out and arm
in signaling between frames or other test equipment. The
TRIGGER OUT is a simple three- state LVTTL 50
Ω
line
drive circuit. TRIGGER IN (ARM) is complicated by the
need to handle variable threshold levels. The circuit consists