ADLINK Technology LittleBoard 735, Справочное руководство

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Chapter 3 Hardware
LittleBoard 735 Reference Manual 33
LVDS Interface
Table 3-15 describes the pin signals of the LVDS interface, which uses 30 pins, 2 rows, odd/even sequence
(1, 2) with 0.079" (2mm) pitch.
Note: The shaded areas denote power or ground.
Table 3-15. LVDS Interface Pin Signals (J26)
Pin # Signal Description Line Channel
1 +12V +12 volt input
NA NA
2 +VCC (+3.3V/+5V) JP1 determines voltage on pin
3 GND Ground
4 GND Ground
5 LBCLK_P Clock Positive Output Clock
Channel 2
6 LBCLK_N Clock Negative Output
7 Not Supported N/A N/S
8 Not Supported N/A
9 LBDATA2_P Data Positive Output 2
10 LBDATA2_N Data Negative Output
11 LBDATA1_P Data Positive Output 1
12 LBDATA1_N Data Negative Output
13 LBDATA0_P Data Positive Output 0
14 LBDATA0_N Data Negative Output
15 LVDS_BKLT_CTL Control Panel Backlight NA NA
16 LVDD_EN Enable Panel Power NA NA
17 LACLK_P Clock Positive Output Clock
Channel 1
18 LACLK_N Clock Negative Output
19 Not Supported N/A N/S
20 Not Supported N/A
21 LADATA2_P Data Positive Output 2
22 LADATA2_N Data Negative Output
23 LADATA1_P Data Positive Output 1
24 LADATA1_N Data Negative Output
25 LADATA0_P Data Positive Output 0
26 LADATA0_N Data Negative Output
27 L_DDC_CLK Display Data Channel Clock NA NA
28 L_DDC_DAT Display Data Channel Data NA NA
29 LVDS_BKLT_EN Enable Backlight Inverter NA NA
30 NC Not Connected NA NA
NOTE Pins 5-14 constitute 2
nd
channel interface of two channels. Pins 15-26 constitute
1
st
channel interface of two channels, or a single channel interface.