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AT-1120 User Guide and Specifications - 30 -

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Running the Host VI

1.

Connect one end of an SMA cable to AO 0+ on the front panel of the AT 1120 and the other
end to the oscilloscope (50

Ω

input).

2.

Tap the unused input (AO 0-)with a 50

Ω

load.

3.

Open the front panel of

GenerateSine1120(Host).vi.

4.

Click the Run button to run the VI.

5.

Wait for module initialization.

6.

The AT-1120 generates one 128 points sine waveform.

7.

Click the STOP button on the front panel to stop the module and the VI.

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Содержание AT-1120

Страница 1: ...t High Speed Signal Generator Adapter Module for NI FlexRIO User Manual January 2013 Rev 1 3 Active Technologies S r l Via Bela Bartok 29 B 44124 Ferrara ITALY Tel 39 0532 91456 Fax 39 0532 970134 Internet www activetechnologies it E mail info activetechnologies it 2013 by Active Technologies All rights reserved ...

Страница 2: ...PGA I O Interface 11 Clocking Scheme 12 Cables 12 LabView Interface 13 LabView Interface Host Side 16 Software Prerequisites 18 Example Code Review for AT 1120 adapter module 18 DACModuleControl Host exe 18 GeneratePulse Host vi 21 DDS and Trigger Route vi 22 Using Your AT 1120 with a LabVIEW FPGA Example VI 23 Creating a Host VI on an FPGA Target 26 Running the Host VI 30 Creating a Custom FPGA T...

Страница 3: ... User Guide and Specifications 3 www activetechnologies it Configuration EEPROM Map 36 Electromagnetic Compatibility 36 CE Compliance 37 Appendix Installing EMI Controls 38 Installing PXI EMC Filler Panels 38 ...

Страница 4: ...ls using a LabVIEW FPGA example VI and how to create and run your own LabVIEW project with the AT 1120R Note Before configuring your AT 1120 you must install the appropriate software and hardware Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation instructions Figure 1 shows an example of a properly connected NI FlexRIO device Figure 1 NI FlexRIO Device Note ...

Страница 5: ... minimize the potential for the product to cause interference to radio and television reception or to experience unacceptable performance degradation install and use this product in strict accordance with instructions in the product documentation Furthermore any changes or modifications to the product not expressly approved by Active Technologies could void your authority to operate it under your ...

Страница 6: ...ion Guide and Specifications Available in your FPGA module hardwarekit and from the Start Menu Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module NI Adapter Module User Guide and Specifications Available in your adapter module hardwarekit and from the Start Menu Contains signal information examples and specifications for your adapter module LabVIE...

Страница 7: ...AT 1120 User Guide and Specifications 7 www activetechnologies it These documents are also available at ni com manuals ...

Страница 8: ...e AT 1120 before powering down the module and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module Device Front Panel Connector Signal Description TRIG IN SMA input connector for Trigger IN TRIG OUT SMA output connector for Trigger Out AO 0 Differential analog output channel 0 AO 0 Differential analog output channel 0 CLK IN SMA input connector for extern...

Страница 9: ...that exceed any of the maximum ratings of any connector on the AT 1120R can damage the device and the chassis Active Technologies is not liable for any damage resulting from such signal connections For the maximum input and output ratings for each signal refer to the Specifications sheet ...

Страница 10: ...on functionality of the user defined CLIP but it also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface Figure 4 shows the relationship between an FPGA VI and CLIP NI FlexRIO FPGA Module FPGA User Defined CLIP User Defined CLIP LabV...

Страница 11: ...a Clock Generator circuit that provides the 2 GHz clock to the DAC the clock generator source clock can be provided by 25 MHz onboard TCXO or by PXI_e DSTAR A backplane connection The uController write read the DAC parameters the Clock Gen registers and control the multiplexer output It performs also the Power up sequencing This CLIP provides read write access to all FPGA look up tables that are i...

Страница 12: ...ock rate 125 MHz the datadac_ch0_in1 datadac_ch0_in15 are internally serialized by 8 to obtain a data rate of 1GS s datai2c0 datai2c5 Input Data transferred by I2C write readdataI2C Output Data retrieved by I2C read startRDI2C Input Start I2C bus read startWRI2C Input Start I2C bus write reset_in Input Reset the DCMs and FAM lockedfast Output Check if the FPGA DCM has locked or not trig_in Output ...

Страница 13: ...500 MHz and 125 MHz clocks to the OSerdes and FlexRIO interface If the user selects Internal and From FPGA Clock the FAM takes the 125M from the PXI Express backplane so the user should provide the clock through DSTARA clock by using the NI timing board If the user selects External the DAC clock 2 GHz has to be provided by outside using the SMA CLK IN bypassing the clock generator circuit Componen...

Страница 14: ...nally serialized by 8 to obtain a data rate of 1GS s PORT 2 DATA The LabView interface of the CLIP reads data from the look up tables Memory8 Memory16 at IO Module Clock rate 125 MHz the datadac_ch0_in8 datadac_ch0_in15 are internally serialized by 8 to obtain a data rate of 1GS s The Clip provides also access to DDS Arbitrary mode selection Clock Selection Trigger In and Trigger Out resources and...

Страница 15: ...DATA Memory data Write Address Memory address ClockSEL Select the clock source for DAC OSerdes If false it selects the Inst_DCM_CLOCK_DIV4 outputs if true it selects the Inst_PLL DCM clock outputs The user should set it to false if he needs to use the TCXO onboard clock or set it to true if he needs to use the clock coming from the Timing Board PXIe backplane ClkEnable It enables the FPGA DCM cloc...

Страница 16: ...sfer StartWRI2c Start I2c write transfer 1 In DDS mode the lookup table contains one cycle of the waveform to be generated and typically contains 1024 to 8192 sample points which represent the waveform For our examples we are using a 2048 sample reference waveform representing one cycle of our repetitive waveform The core component of a DDS waveform generator is the accumulator The accumulator is ...

Страница 17: ...be true To enter in Debug mode set DEBUG as true Input Parameters FPGA VI Reference IN FPGA reference RIO Device CLOCK SELECTION DAC Clock source selection INTERNAL CLOCK Clock Generator input source Error in Output Parameters FPGA DCM LOCKED if true the FPGA DCM has locked DAC A Aligned if true the DAC has been correctly initialized and aligned Error out IMPORTANT NOTE the user should NOT hit the...

Страница 18: ... look up tables reading see section above Input parameters NumSamples the waveform length in samples DDS ARB DDS false or Arbitrary true generation mode FSampleDAC DAC sampling rate FoutDDS DDS waveform frequency requested by the user The vi calculates the Increment parameter using FSampleDAC and FoutDDS resource name FlexRIO resource name error in Output parameter error out StartGeneration Host v...

Страница 19: ...12 Example Code Review for AT 1120 adapter module DACModuleControl Host exe Software requirements Labview 2012 Modulation Toolkit This LabView application gives the user full access to all the main 1120 1212 features The control panel provides a waveform generator style approach to the FAM allowing to set the parameters of the signals that will be load and generated by the FAM The source file DACM...

Страница 20: ...ltiple of 16 duty cycle amplitude from 0 to 8191 b phase and number of cycles related to the waveform output frequency c Waveform type and the standard deviation of the gaussian noise that it is possible to add to the waveform The user can also import a waveform from file or generate a Chirp pattern BPSK signals and QAM modulation adding AWGN IQ Impairments Phase Noise to the output pattern Press ...

Страница 21: ...the source clock for the Clock Generator circuit It can be From Oscillator onboard TCXO or From FPGA Clock from PXIe Backplane DSTARA Timing board DDS mode waveform generation parameters When the FAM works in DDS mode the user should upload a 2048 samples waveform and set its parameters using DDS frequency Sweep Freq Incr and Sweep Freq Max controls It is also possible to generate a frequency swee...

Страница 22: ...tion select the DAC clock source It can be Internal from Clock Generator circuit or External from SMA connector 2GHz Internal Clock Source select the source clock for the Clock Generator circuit It can be From Oscillator onboard TCXO or From FPGA Clock from PXIe Backplane DSTARA Timing board Set the NumSamples the samples number of the pulse waveform It must be multiple of 16 Module Init OK indica...

Страница 23: ...e 6674T NI Timing board and to the DSTARA DSTARB clock global trigger routing Set the DDS frequency to 125 MHz and fill the Destination Terminal Array The Destination Terminal Array should contain all the PXIe_DSTARA connection to the FlexRIO boards that will provide the same reference clock to the adapter module refer to the chassis manual Fill the Destination Trigger Array with the PXIe_DSTARB g...

Страница 24: ...RIO Adapter Module Support software includes a variety of example projects to help get you started creating your LabVIEW FPGA application This section explains how to use an existing LabVIEW FPGA example project to generate signals with the AT 1120 This example requires at least one SMA cable for connecting signals to your AT 1120 Note The examples available for your device are dependent on the ve...

Страница 25: ...H in the Adapter Name pull down menu 7 Select AO 0 in the Selected Channel pull down menu 8 Select ARB in the DDS ARB control 9 Select Internal in the Clock Selection pull down menu and From Oscillator in the Internal Clock Source pull down menu 10 Click the Run button to run the VI 11 Wait until Module Ready and DAC Aligned leds become green 12 Select the Waveform you want to generate by using Wa...

Страница 26: ... Guide and Specifications 25 www activetechnologies it 15 Press the RUN SELECTED CH button to start the waveform generation 16 Press the STOP button to stop the generation 17 Press the EXIT VI button to stop the VI ...

Страница 27: ...Graph indicator in the front panel 3 Add the RIO Device control located on Modern I O palette 4 Add a STOP button located on Express Buttons Switches 5 Add a LED indicator INIT OK located on Express LEDs 6 Select Window Show Block Diagram to open the VI block diagram 7 Add a Stacked Sequence Structure 8 Place the GetFPGA1120Reference vi to get the reference to the 1120 FPGA Target AT_HS_Signal_Gen...

Страница 28: ...case structure The FPGA DCM Locked and DAC A Aligned monitor if the initialization stage has been correctly terminated 12 Add a Frame After in the stacked sequence we will generate the waveform samples 13 Add Sine Pattern vi from Signal Generation Palette 14 Samples 128 Amplitude 4000 Cycle 1 Phase 0 add 8192 to the waveform array and connect the samples array to the Waveform Graph If the VI execu...

Страница 29: ...e will load the generated samples into the channels module 16 Add a For Loop structure and wire 2 to the Loop count 17 Place the WriteTables Host vi located on AT_HS_Signal_Generator 1120 Module folder Connect the RIO Device and WavefArray like in the picture below 18 Add a Frame After in the stacked sequence we will start the waveform generation 19 Add a Flat Sequence Structure ...

Страница 30: ...1120 Module folder Connect the SYNC False 22 Add a Frame After in the stacked sequence 23 Add a While Loop structure and a Case structure inside the loop 24 Place an Event Structure inside a While Loop Connect and Add an Event Case on the Stop button value change Place the StopGeneration Host vi located on AT_HS_Signal_Generator 1120 Module folder Connect the FPGA VI Reference IN FPGA Reference an...

Страница 31: ... the AT 1120 and the other end to the oscilloscope 50 Ω input 2 Tap the unused input AO 0 with a 50Ω load 3 Open the front panel of GenerateSine1120 Host vi 4 Click the Run button to run the VI 5 Wait for module initialization 6 The AT 1120 generates one 128 points sine waveform 7 Click the STOP button on the front panel to stop the module and the VI ...

Страница 32: ... Device option button and expand FPGA Target The target is displayed 3 Select your device and click OK The target and target properties are loaded into the Project Explorer window 4 Right click FPGA Target in the Project Explorer window and select New FPGA Base Clock Select the IO Module Clock 0 resource Compile for single frequency and set the frequency at 125 MHZ Click OK 5 Right click FPGA Targ...

Страница 33: ... select DStarA Clock as clockin and 40 MHz Onboard Clock as clockin40m Click OK 11 Copy the Memory1 element in the FPGA Target 1212 and paste it in the FPGA Target you have just created 12 Right click the FPGA Target and select New VI to create a VI for the FPGA 13 In the Project Explorer window expand the IO Module tree view 14 Add a Timed Loop as shown in the figure below and right click to open...

Страница 34: ... in the figure below and right click to open the LabView palette Select the FPGA I O palette and add an I O node 18 Wire the datadac_ch0_in0_ datadac_ch0_in15 connectors as in the picture above 19 Wire the IO Module Clock 0 to the clock loop 20 Right click to open the LabView palette Select the Memory FIFO palette and add a Memory Method node Right click on the Memory method Select Memory Memory1 ...

Страница 35: ...odule is stopped The second case checks if the last address of the Memory1 2047 has been reached If true it puts the memory address to the initial value 0 24 Save the VI Running the Host VI 1 Connect one end of an SMA cable to AO 0 on the front panel of the AT 1120 and the other end to the oscilloscope 50 Ω input 2 Tap the unused input AO 0 with a 50Ω load 3 Open the front panel of CustomFPGAExamp...

Страница 36: ... the user needs Mini Circuit RLP 470 Mini Circuit SBPL 467 Maximally Flat Group Delay Mini Circuit SCLF 550 Mini Circuit SLP 550 Mini Circuit VLF 530 Mini Circuit VLFX 500 Mini Circuit SBPL 933 Maximally Flat Group Delay Calibration Service for AT 1120 OPTIONAL Perform the calibration procedure Store the calibration parameters into the EEPROM module Verification of measurements according to specif...

Страница 37: ...duct performance that are not covered by warranty Typical values cover the expected performance of units over ambient temperature ranges of 23 5 C with an 95 confidence level based on measurements taken during development or production Configuration EEPROM Map Byte Address Size Bytes Field Name 0x0 2 Vendor ID 0x2 2 Product ID 0x4 4 Serial Number 0x20 14 Calibration Parameters Total power typical ...

Страница 38: ...direct method CEI EN 61000 4 3 Radiated RF electro magnetic field immunity test Level 10V m mod 1kHz AM 80 at 3m of distance frequency range 80 1000MHz Level 3V m mod 1kHz AM 80 at 3m of distance frequency range 1 4 2 0 GHz Level 1V m mod 1kHz AM 80 at 3m of distance frequency range 2 0 2 7 GHz CE Compliance This product meets the essential requirements of applicable European Directives as follows...

Страница 39: ... FPGA Module Installation Guide and Specifications Installing PXI EMC Filler Panels Complete the following instructions to install PXI EMC filler panels National Instruments part number 778700 01 in your PXI chassis 1 Remove the captive screw covers 2 Install the PXI EMC filler panels by securing the captive mounting screws to the chassis as shown in Figure 15 Make sure that the EMC gasket is on t...

Страница 40: ...Note You must populate all slots with a module or a PXI EMC filler panel to ensure proper module cooling Do not over tighten screws 2 5 lb in maximum For additional information about the use of PXI EMC filler panels in your PXI system visit ni com info and enter emcpa ...

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