Active Technologies AT-1120, Руководство пользователя

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AT-1120 User Guide and Specifications - 12 - www.activetechnologies.it
Timing Board (PXIe backplane).
Clocking Scheme
The DAC clock can be sourced from the internal Clock Generator circuit on the adapter module or
from the outside using the SMA CLK IN (external clock).
The Clock Generator clock can be sourced from the internal TCXO oscillator (25 MHz) or from the PXI
Express backplane clock.
In software, use the
ClockSelection.vi to select from the different clock sources.
If the user selects Internal and From Oscillator , the 25 MHz onboard TCXO will provide the clock to
the Clock Generator input. The clock generator generates 2GHz, the DAC divides it by 4 and it
provides 500 MHz clock to FlexRIO FPGA.
The BUFR and PLL_125M instances divide the 500 MHz clock by 4 and provide the 500 MHz and 125
MHz clocks to the OSerdes and FlexRIO interface.
If the user selects Internal and From FPGA Clock , the FAM takes the 125M from the PXI Express
backplane, so the user should provide the clock through DSTARA clock by using the NI timing board.
If the user selects External , the DAC clock (2 GHz) has to be provided by outside using the SMA CLK IN
bypassing the clock generator circuit.
Component Level IP Clocks
Name Connection
Clockin
DSTAR Clock (125 MHz): see above for clocking
scheme usage.
Warning : on the NI PXIe-7966R the DSTAR Clock
frequency should be set at 124.98MHz.
Clockin40m 40 MHz FlexRIO Clock: used on the LabView
interface of the clip (ReadWriteTablesTest.vi)
IO Module Clock 125 MHz clock from FAM
Cables
Use any shielded 50 Ω coaxial cable with an SMA plug end to connect to the AO 0+, AO 0, TRIG IN,
TRIG OUT and CLK IN connectors on the AT-1120 front panel.
For more information about connecting I/O signals on your device, refer to the
Specifications sheet.