AT-1120 User Guide and Specifications - 11 -
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FPGA I/O Interface
datadac_ch0_in0,datadac_ch0_in2,
datadac_ch0_in4,datadac_ch0_in6,
datadac_ch0_in8,datadac_ch0_in10,
datadac_ch0_in12,datadac_ch0_in14
Input[13..0]
Data for DAC Port 1.
The user needs to send data to the Clip Inputs
at IO Module Clock rate (125 MHz); the
datadac_ch0_in0..datadac_ch0_in14 are
internally serialized by 8 to obtain a data rate
of 1GS/s.
datadac_ch0_in1,datadac_ch0_in3,
datadac_ch0_in5,datadac_ch0_in7,
datadac_ch0_in9,datadac_ch0_in11,
datadac_ch0_in13,datadac_ch0_in15
Input[13..0]
Data for DAC Port 2.
The user needs to send data to the Clip Inputs
at IO Module Clock rate (125 MHz); the
datadac_ch0_in1..datadac_ch0_in15 are
internally serialized by 8 to obtain a data rate
of 1GS/s.
datai2c0..datai2c5
Input
Data transferred by I2C write
readdataI2C
Output
Data retrieved by I2C read
startRDI2C
Input
Start I2C bus read
startWRI2C
Input
Start I2C bus write
reset_in
Input
Reset the DCMs and FAM
lockedfast
Output
Check if the FPGA DCM has locked or not
trig_in
Output
Check if the SMA Trigger IN signal is high or
low
trig_out
Output
Send the Trigger Output to the FAM
clkenable
Input
Enable/Disable the FPGA DCM clock outputs
clocksel
Input
Select the clock source for DAC/OSerdes. If
false, it selects the Inst_DCM_CLOCK_DIV4
outputs; if true it selects the Inst_PLL DCM
clock outputs.
The user should set it to false if he needs to
use the TCXO onboard clock or set it to true if
he needs to use the clock coming from the
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