Active Technologies AT-1120, Руководство пользователя

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AT-1120 User Guide and Specifications - 13 - www.activetechnologies.it
LabView Interface
Target Side - ReadWriteTablesTest.vi
The DAC contains two parallel LVDS input ports consisting of 14 differential LVDS signals DB[13:0].
Each data port runs internally at half the speed of the DAC Clock (2 GHz), so the user needs to
guarantee them the correct data rate.
PORT 1 DATA
The LabView interface of the CLIP reads data from the look up tables (Memory1..Memory7) at IO
Module Clock rate (125 MHz); the datadac_ch0_in0..datadac_ch0_in7 are internally serialized by 8 to
obtain a data rate of 1GS/s.
PORT 2 DATA
The LabView interface of the CLIP reads data from the look up tables (Memory8..Memory16) at IO
Module Clock rate (125 MHz); the datadac_ch0_in8..datadac_ch0_in15 are internally serialized by 8
to obtain a data rate of 1GS/s.
The Clip provides also access to DDS/Arbitrary mode selection,Clock Selection, Trigger In and Trigger
Out resources and START Generation command.
The Clip has a built in I2C bus interface that we developed to speed up the I2C transfers.
The user has to load each look-up tables with the same waveform and the CLIP reads them updating
the Start/Stop Address and Increment parameters to convey parallel data stream at the converter at
high speeds.