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Actel ProASIC3/E Скачать руководство пользователя страница 71

ProASIC3/E Starter Kit User’s Guide and Tutorial

71

A

PQ208 Package Connections for A3PE600 and
A3P250 Devices

Due to the comprehensive and flexible nature of ProASIC3 device user I/Os, a naming scheme is used to show the
details of the I/O. The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity for
differential I/Os.

Figure A-1 on page 72

Table A-1 on page 72

are extracted from the ProASIC3 and ProASIC3E datasheets and

provide package connections for the A3P250 and A3E600 devices. Pinouts for other devices in the PQ208 family may
be found on the Actel website:

ProASIC3 Flash Family FPGAs datasheet at

www.actel.com/documents/PA3_DS.pdf

ProASIC3E Flash Family FPGAs datasheet at

www.actel.com/documents/PA3E_DS.pdf

These datasheets are included on the ProASIC3 and ProASIC3E Starter Kit CD. However, the website should always
be referenced for access to the most recent datasheet.

I/O Nomenclature

= Gmn/IOuxwBy

Gmn is only used for I/Os that also have CCC access – i.e., global pins.

G = Global

m = Global pin location associated with each CCC on the device: A (northwest corner), B

(northeast corner), C (east middle), D (southeast corner), E (southwest corner), and F (west
middle)

n = Global input MUX and pin number of the associated Global location m, either A0, A1,A2,

B0, B1, B2, C0, C1, or C2

u = I/O pair number in the bank, starting at 00 from the northwest I/O bank in a clockwise

direction

x = P (Positive) or N (Negative) for differential pairs, or S (Single-Ended) for the I/O that

support single-ended and voltage-referenced I/O standards only

w = D (Differential Pair) or P (Pair) or S (Single-Ended). D (Differential Pair) if both members

of the pair are bonded out to adjacent pins or are separated only by one GND or NC pin; P
(Pair) if both members of the pair are bonded out but do not meet the adjacency
requirement; or S (Single-Ended) if the I/O pair is not bonded out. For Differential (D)
pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal adjacency
does not meet the requirements for a true differential pair.

B = Bank

y = Bank number [0..3] for ProASIC3 and [0..7] for ProASIC3E. Bank number starting at 0

from the northwest I/O bank in a clockwise direction

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Содержание ProASIC3/E

Страница 1: ...ProASIC3 E Starter Kit User s Guide and Tutorial...

Страница 2: ...fitness for a particular purpose Information in this document is subject to change without notice Actel assumes no responsibility for any errors that may appear in this document This document contains...

Страница 3: ...ons 18 FPGA LCD Interface 19 LCD Power Supply Circuit 20 LVDS Channels 20 3 Setup and Self Test 23 Software Installation 23 Hardware Installation 23 Testing the Evaluation Board 23 Programming the Tes...

Страница 4: ...edures for Board Testing 67 Overview 67 Equipment Required 67 Test Procedure for the A3PE A3P EVAL BRD1 67 A PQ208 Package Connections for A3PE600 and A3P250 Devices 71 208 Pin PQFP 72 B Board Schemat...

Страница 5: ...DL ProASIC3 E Design Flow introduces the design flow for VHDL using the Actel Libero Integrated Design Environment IDE suite Chapter 7 Quick Start Tutorial illustrates a VHDL design for a ProASIC3 E s...

Страница 6: ......

Страница 7: ...Kit Contents The starter kit includes the following ProsASIC3 E Evaluation Board Libero IDE Gold FlashPro3 The ProASIC3 E Starter Kit User s Guide Tutorial CD with design examples Switching brick powe...

Страница 8: ......

Страница 9: ...witches to provide four inputs each to the FPGA and which are set to a user switchable hexadecimal input value Large LCD alphanumeric display to facilitate detailed message outputs from the FPGA appli...

Страница 10: ...with the Starter Kit The schematics are also available for download from the Actel website The electronic versions of the dedicated schematics can naturally be enlarged to a far greater degree than ca...

Страница 11: ...lowest possible power consumption for the part Perpetually powering the PLL lines would not achieve that 3 It is easy to connect the appropriate pins together when desired That is why we make the pin...

Страница 12: ...emonstrating LVDS extended I O bank capability The presence of these voltages is indicated by four green LEDs D13 D9 D10 and D11 respectively illuminating at the top right of the board Each LED is lab...

Страница 13: ...connection pin interspersing the voltage pins This prevents accidental use of a jumper to short a supply rail to ground which could connect differing supply rails together The purpose is not to prote...

Страница 14: ...f the board If it does not contain green wire it is an original Rev2 To chain Rev2 boards together If reworked treat it as Rev3 in the previous section If not reworked then chaining of the boards cann...

Страница 15: ...ble indicated by the red ribbon running along the side of the cable will be on the left side as it enters into the board After connecting the FlashPro3 programmer select Analyze Chain from the File me...

Страница 16: ...These test points are labeled on the silkscreen as TP1 TP2 etc All such test points are also labeled on the silk screen with the voltage expected to be observed at that test point Voltages will be on...

Страница 17: ...e Should better stability be required an external oscillator may be provided via the SMA connector Typically a TCXO will give 1 ppm stability and an OCXO will give 0 1 ppm stability Both the default o...

Страница 18: ...witch drives a 1 into the device The 1 continues to drive while the switch is in place Releasing a switch drives a zero into the device Table 2 2 lists the switch device connections To use the device...

Страница 19: ...lines are driven from BANK0 I O lines of FPGA These BANK0 I O lines of FPGA are configured as LVTTL outputs for driving the LCD Both VCCI and VMV power points of Bank0 are from a fixed 3 3 volts sour...

Страница 20: ...rolled by SW11 Note SW11 also controls U11 and hence all the board regulator power supplies The presence of the LCD power supply 5 V from U20 is indicated by the LED D17 The glowing of D17 indicates t...

Страница 21: ...T 5E on Ethernet type connectors The connections on the CAT 5E SECONDARY are reversed so as to allow a standard patch cable to check loopback on these LVDS signals A 1 foot CAT5 standard patch cable s...

Страница 22: ...DB7V1 TX1 CAT 5E PRI 1 8 IO132NDB7V1 TX1 CAT 5E PRI 2 9 IO130PDB7V1 TX2 CAT 5E PRI 5 10 IO130NDB7V1 TX2 CAT 5E PRI 4 11 IO127PDB7V1 RX1 CAT 5E PRI 3 12 IO127NDB7V1 RX1 CAT 5E PRI 6 13 IO126PDB7V0 RX2...

Страница 23: ...www actel com documents flashpro_ug pdf Testing the Evaluation Board Refer to Test Procedures for Board Testing on page 67 Programming the Test File To retest the evaluation board at any time use the...

Страница 24: ......

Страница 25: ...can switch between the data using the SW6 signal The counter has a synchronous load and an asynchronous clear A block diagram of the Data_Block is shown in Figure 4 2 Figure 4 2 Data Block Diagram CL...

Страница 26: ...2 Up Down Control for the 8 bit counter Press and hold SW2 for down count Press SW3 Synchronous load for the 8 bit counter Press SW3 for loading from the Hex switches Press SW4 Switching between manua...

Страница 27: ...ProASIC3 E Starter Kit User s Guide and Tutorial 27 The state diagram is shown in Figure 4 3 Figure 4 3 LCD State Diagram setmode2 home2 home1 write1 setmode1 clear2 clear1 setfund warmup...

Страница 28: ......

Страница 29: ...ents are taken using a 1159A 1GHz Agilent differential probe Design Figure 5 1 on page 29 shows the block diagram of the transmitter section of the test design programmed inside the Proasic3 FPGA As s...

Страница 30: ...l Measurement Results Figure 5 2 shows the LVDS signal across the 100 Ohm termination resistor at 300 Mb s Figure 5 2 shows that the eye height across the termination is about 275 mV which is well wit...

Страница 31: ...gn Entry Design Implementation Programming System Verification Logic NavigatorTM Actel Device Design Creation Verification Design Implementation System Verification Programming Silicon Sculptor only a...

Страница 32: ...generates a symbol for the selected HDL block The macro is accessible from the components list in ViewDraw for Actel Test Bench Generation It is necessary to create a test bench and associate it with...

Страница 33: ...nd route perform the post layout timing simulation For more information on the tools described in the above section refer to the Designer User s Guide Programming Program the device with programming s...

Страница 34: ......

Страница 35: ...Simulation with Back Annotated Timing Step 7 Generate the Programming File Step 8 Program the Device Step 1 Create a New Project This step uses the Libero IDE HDL Editor to enter an Actel VHDL design...

Страница 36: ...lect your project Family Die and Package For this tutorial you can select ProASIC3E the A3PE600 die and 208 PQFP for the package Figure 7 2 or select ProASIC3 the A3P250 die and 208 PQFP for the packa...

Страница 37: ...default tools included with Libero IDE 9 Click the Add button to add a different Synthesis Simulation or Stimulus tool If you wish to add a tool Libero IDE opens the Add Profile dialog box Figure 7 5...

Страница 38: ...13 Select the file type and click Add Files Browse to your file and click Add Add as many files as you wish in this way Click Next to continue 14 Review your project information Click Finish to close...

Страница 39: ...opens Enter the following VHDL file or if this document is open in an electronic form copy and paste it from here library IEEE use IEEE std_logic_1164 all use IEEE std_logic_arith all use IEEE std_lo...

Страница 40: ...nd Clock 1 then if Updown 0 then Qaux Qaux 1 else Qaux Qaux 1 end if end if end process Q std_logic_vector Qaux end behavioral 3 From the File menu click Save The design file counter appears in the De...

Страница 41: ...n the design hierarchy and select Set As Root so that Top vhd is represented as the top level file for the project You can import all the files from the Libero IDE menu using File Import Files Figure...

Страница 42: ...e active state is the type of waveform that is drawn next Click a state button to activate it The state buttons automatically toggle between the two most recently activated states The state with the s...

Страница 43: ...re 7 14 Block Copy Waveforms Dialog Box 3 Enter the values that define the copy and paste 4 Select either Time or Clock cycle for the base units of the dialog Remember the following When copying only...

Страница 44: ...Click OK to complete the copy and paste operation Export the Testbench In this step you create a stimulus file for the design and generate a testbench using WaveFormer Lite After exporting the testbe...

Страница 45: ...ers Figure 7 16 Set a frequency of 40 MHz Figure 7 16 Edit Clock Parameters in WaveFormer Lite This creates the waveform shown in Figure 7 17 Figure 7 17 WaveForm Timing Diagram 3 Click the HIGH state...

Страница 46: ...lect Save As from the File menu In the Save As dialog box enter test_tbench btim as the file name and click Save 8 After saving the timing diagram file select Export Timing Diagram As from the Export...

Страница 47: ...or 3 Create the VHDL testbench and save it Pre Synthesis Simulation Once you generate a testbench use ModelSim to perform a pre synthesis simulation To perform a pre synthesis simulation Right click T...

Страница 48: ...with them 6 Click the Simulation icon in the Design Flow window or right click Top in the Design Hierarchy tab and select Run Pre Synthesis Simulation as shown in Figure 7 22 Figure 7 22 Run Pre Synt...

Страница 49: ...h Scroll in the Wave window to verify that the design functions properly Figure 7 24 ModelSim Wave Window 8 In the ModelSim window select File Quit to close the window Step 3 Synthesize the Design in...

Страница 50: ...ick the Top vhd file in the Design Hierarchy and select Synthesize This launches the Synplify synthesis tool with the appropriate design files as shown in Figure 7 25 Figure 7 25 Synplify Main Window...

Страница 51: ...Top edn The resulting Top edn file is then automatically translated by Libero IDE into a VHDL netlist called Top vhd The resulting EDIF and VHDL files are displayed under Implementation Files in the F...

Страница 52: ...er works correctly Use the zoom buttons to zoom in and out as necessary Step 5 Implement the Design with Designer After creating and testing the design the next phase is implementing the Design using...

Страница 53: ...tion Wizard A3PE600 2 Select A3P250 in the Die field and select 208 PQFP in the Package field Accept the default Speed grade and Die Voltage and click Next 3 Use the default I O settings and click Nex...

Страница 54: ...ssfully completed 6 Once the design compiles successfully use the I O Attribute Editor tool to assign the pin for subsequent place and route runs Click the I O Attribute Editor to open the tool It ope...

Страница 55: ...it in the src folder Choose pdc for Files of type click Top pdc and Import Figure 7 34 Import PDC File 11 Click OK in the Import Source Files window You need to re Compile the design once a new PDC fi...

Страница 56: ...r click Layout This opens the Layout Options dialog box shown in Figure 7 35 Figure 7 35 Layout Options Dialog Box 13 Click OK to accept the default layout options This runs place and route on the des...

Страница 57: ...igner Step 6 Perform Timing Simulation with Back Annotated Timing After completing the place and route and back annotation of the design perform a timing simulation with the ModelSim HDL simulator To...

Страница 58: ...8 Program the Device After generating the programming file program the device using an Actel FlashPro3 programmer Initial Setup Before performing any action with the FlashPro3 programmer it must be pr...

Страница 59: ...guration list select ProASIC3 E 4 Click Connect A successful connection or any error appears in the Log window as shown in Figure 7 40 Figure 7 40 FlashPro3 Successful Connection Analyze Chain and Dev...

Страница 60: ...If you have an A3P250 device on board you will see the message shown in Figure 7 42 Figure 7 42 FlashPro3 Analyzing Chain A3PE250 3 Select the A3PE600 or the A3P250 from the Device list If only one de...

Страница 61: ...log Box 2 Browse to your Libero IDE project designer impl1 folder select the STAPL file and click Open The FlashPro software loads the file Note You can also find a copy of the Top stp file in the src...

Страница 62: ...ts in Exit 0 PROGRAM Programs the device DEVICE_INFO Displays the serial number of the device the Design Name that is programmed into the device and the checksum that is programmed into the device ERA...

Страница 63: ...are required for programming and cannot be changed 5 Click Execute to start programming The progress of the programming action displays in the Log window The message Exit 0 indicates that the device h...

Страница 64: ...t the verification process A successful verification will result in Exit 0 as shown in Figure 7 48 on page 64 If the STAPL file is different from the file used for programming Exit 11 will appear in t...

Страница 65: ...oftware saves the file Check Functionality of Tutorial Design After programming the device you will see ACTEL A3PE STARTER KIT display on the LCD panel as well as flashing LEDs There are 6 switches SW...

Страница 66: ......

Страница 67: ...r testing of the board Digital Multimeter to measure voltages on the circuit board at the known test points Test Procedure for the A3PE A3P EVAL BRD1 In this section full test procedure for the boards...

Страница 68: ...mmended to do opposite corners first so as to lessen rotational torque on the part 7 Switch on SW11 to the ON position slide it to the right 8 Validate that all 5 LEDs at the top of the board includin...

Страница 69: ...f incorrect VJTAG is reported then remove the jumper placed at J5 and place it instead at J12 across pins 11 and 12 It may safely be left there Repeat the Analyze Chain command If a message appears in...

Страница 70: ......

Страница 71: ...e CCC access i e global pins G Global m Global pin location associated with each CCC on the device A northwest corner B northeast corner C east middle D southeast corner E southwest corner and F west...

Страница 72: ...QFP Figure A 1 208 Pin PQFP Table A 1 Device Connections for 208 Pin PQFP 208 Pin PQFP Pin Number A3PE600 Function A3P250 Function 1 GND GND 2 GNDQ GAA2 IO118PDB3 3 VMV7 IO118NDB3 4 GAB2 IO133PSB7V1 G...

Страница 73: ...111PDB3 20 IO121PSB7V0 IO111NDB3 21 IO122NPB7V0 GFC1 IO110PDB3 22 GFC1 IO120PSB7V0 GFC0 IO110NDB3 23 GFB1 IO119PDB7V0 GFB1 IO109PDB3 24 GFB0 IO119NDB7V0 GFB0 IO109NDB3 25 VCOMPLF VCOMPLF 26 GFA0 IO118...

Страница 74: ...2PPB6V0 GEB0 IO99NDB3 48 GEB0 IO103NPB6V0 GEA1 IO98PDB3 49 GEA0 IO102NPB6V0 GEA0 IO98NDB3 50 VMV6 VMV3 51 GNDQ GNDQ 52 GND GND 53 VMV5 NC 54 GNDQ NC 55 IO101NDB5V2 GEA2 IO97RSB2 56 GEA2 IO101PDB5V2 GE...

Страница 75: ...0 IO79RSB2 78 IO82NPB5V0 IO78RSB2 79 IO83PPB5V0 IO77RSB2 80 IO82PPB5V0 IO76RSB2 81 GND GND 82 IO80NDB4V1 IO75RSB2 83 IO80PDB4V1 IO74RSB2 84 IO79NPB4V1 IO73RSB2 85 IO78NPB4V1 IO72RSB2 86 IO79PPB4V1 IO7...

Страница 76: ...1 VMV3 GDA0 IO60NDB1 112 GDA0 IO67NPB3V1 GDA1 IO60PDB1 113 GDB0 IO66NPB3V1 GDB0 IO59NDB1 114 GDA1 IO67PPB3V1 GDB1 IO59PDB1 115 GDB1 IO66PPB3V1 GDC0 IO58NDB1 116 GDC0 IO65NDB3V1 GDC1 IO58PDB1 117 GDC1...

Страница 77: ...48NDB1 137 IO49NDB2V1 GCC1 IO48PDB1 138 IO49PDB2V1 IO47NDB1 139 IO48PSB2V1 IO47PDB1 140 VCCIB2 VCCIB1 141 GND GND 142 VCC VCC 143 IO47NDB2V1 IO46RSB1 144 IO47PDB2V1 IO45NDB1 145 IO44NDB2V1 IO45PDB1 14...

Страница 78: ...7 IO31NDB1V1 IO32RSB0 168 IO27PDB1V0 IO31RSB0 169 IO27NDB1V0 IO30RSB0 170 VCCIB1 VCCIB0 171 VCC VCC 172 IO23PPB1V0 IO29RSB0 173 IO22PSB1V0 IO28RSB0 174 IO23NPB1V0 IO27RSB0 175 IO21PDB1V0 IO26RSB0 176...

Страница 79: ...GND GND 196 IO07PDB0V1 IO09RSB0 197 IO07NDB0V1 IO08RSB0 198 IO05PDB0V0 IO07RSB0 199 IO05NDB0V0 IO06RSB0 200 VCCIB0 VCCIB0 201 GAC1 IO02PDB0V0 GAC1 IO05RSB0 202 GAC0 IO02NDB0V0 GAC0 IO04RSB0 203 GAB1 I...

Страница 80: ......

Страница 81: ...evel view of the ProASIC3 E Evaluation Board Figure B 2 on page 83 illustrates a bottom level view of the ProASIC3 E Evaluation Board ProASIC3 Schematics The last pages of this appendix show the follo...

Страница 82: ...82 ProASIC3 E Starter Kit User s Guide and Tutorial Figure B 1 Top Level View of ProASIC3 E Evaluation Board...

Страница 83: ...ProASIC3 Schematics ProASIC3 E Starter Kit User s Guide and Tutorial 83 Figure B 2 Bottom Level View of ProASIC3 E Evaluation Board...

Страница 84: ...0 01UF 50V C 1 6 0 01UF 50V VIN 2 ON OFF 7 GND 4 VSW 1 NC 5 CB 3 FB 6 U 1 1 L M 2 6 7 8 S 3 3 U 1 1 L M 2 6 7 8 S 3 3 1 2 3 J 1 8 C O N N _ K L D _ S M T J 1 8 C O N N _ K L D _ S M T 1 2 C 1 5 0 01UF...

Страница 85: ...T i t l e S i z e D o c u m e n t N o D R A W N B Y Rev P g of Actel Corp 2061 Stierlin Ct Mountain View CA 94043 Approvals E n g M g r E n g r Doc Ctrl A s s e m b l y D a t e T i t l e S i z e D o c...

Страница 86: ...t N o D R A W N B Y Rev P g of SCHEMATIC DIAGRAM NOTES 1 UNLESS STATED OTHERWISE A ALL RESISTOR ARE IN OHMS 5 TOLERANCE B ALL CAPACITORS ARE IN MICROFARADS 10 TOLERANCE BOARD INFORMATION PCB FAB REV...

Страница 87: ...3 0 Sanmina SCI ProASIC3 E STARTER KIT BOARD A3PE EVAL BRD600 SA U8 PIN 69 U8 PIN 70 U8 PIN 73 U8 PIN 74 U8 PIN 75 U8 PIN 76 U8 PIN 77 U8 PIN 78 U8 PIN 64 U8 PIN 66 U8 PIN 67 U8 PIN 68 1 2 C 1 7 0 01...

Страница 88: ...C 0 I O 1 0 4 N D B 6 V 0 V M V 1 V M V 2 V M V 3 V M V 6 V M V 7 V M V 0 T 1 T 3 G F B 1 I O 1 1 9 P D B 7 V 0 G F B 0 I O 1 1 9 N D B 7 V 0 G F C 2 I O 1 1 5 P P B 6 V 1 I O 1 1 5 N P B 6 V 1 G F B...

Страница 89: ...V 1 2 C 5 0 1UF 50V C 5 0 1UF 50V 1 2 R 5 3 4 9 9 R 5 3 4 9 9 1 2 R 4 5 2k R 4 5 2k 1 2 R 2 8 1 K R 2 8 1 K 1 2 R 2 9 1 K R 2 9 1 K 1 2 3 J P 2 4 J P 2 4 1 2 R 3 7 1 K R 3 7 1 K 1 2 J P 1 6 J P 1 6 1...

Страница 90: ...2 8 T P O I N T A T P 1 9 T P O I N T A T P 1 9 T P O I N T A 1 3 2 4 J 5 H E A D E R 2 X 2 J 5 H E A D E R 2 X 2 T P 3 9 T P O I N T A T P 3 9 T P O I N T A 12 13 11 U 3 D 7 4 L V C 1 2 5 A P W R U 3...

Страница 91: ...0 01UF 50V 1 2 C 3 8 0 01UF 50V C 3 8 0 01UF 50V 1 2 C 3 0 0 01UF 50V C 3 0 0 01UF 50V T P 7 T P 7 1 2 C 3 5 0 01UF 50V C 3 5 0 01UF 50V 1 2 C 4 7 0 01UF 50V C 4 7 0 01UF 50V 1 2 C 4 2 0 01UF 50V C 4...

Страница 92: ...AB REV 02 PCB ASSEMBLY REV 02 LCD POWER SUPPLY CIRCUIT LVDS SIGNAL ROUTING VIA 1 0 1 0 03 10 05 B 3 0 Sanmina SCI CAT 5E CONNECTORS 5V 500mA Max TX1 TX1 TX2 TX2 TX3 TX3 TX4 TX4 ProASIC3 E STARTER KIT...

Страница 93: ...following layers of copper Layer 1 Top signal layer Layer 2 Ground plane Layer 3 Signal layer 3 used for LVDS receive and other signals Layer 4 Signal layer 4 used for LVDS transmit and other signals...

Страница 94: ...94 ProASIC3 E Starter Kit User s Guide and Tutorial Figure C 1 Layer 1 Top Signal Layer...

Страница 95: ...ProASIC3 E Starter Kit User s Guide and Tutorial 95 Figure C 2 Layer 2 Ground Plane Blank...

Страница 96: ...96 ProASIC3 E Starter Kit User s Guide and Tutorial Figure C 3 Layer 3 Signal 3 LVDS Receive Layer...

Страница 97: ...ProASIC3 E Starter Kit User s Guide and Tutorial 97 Figure C 4 Layer 4 LVDS Transmit Layer...

Страница 98: ...98 ProASIC3 E Starter Kit User s Guide and Tutorial Figure C 5 Layer 5 Power Plane Blank...

Страница 99: ...ProASIC3 E Starter Kit User s Guide and Tutorial 99 Figure C 6 Layer 6 Bottom...

Страница 100: ...100 ProASIC3 E Starter Kit User s Guide and Tutorial Figure C 7 Layer 6 Bottom Viewed from Bottom...

Страница 101: ...echnical Support Center spends a great deal of time creating application notes and answers to FAQs So before you contact us please visit our online resources It is very likely we have already answered...

Страница 102: ...ueue where the first available application engineer receives the data and returns your call The phone hours are from 7 00 A M to 6 00 P M Pacific Time Monday through Friday The Technical Support numbe...

Страница 103: ...flow design creation adding ACTgen macros 32 design capture 32 pre synthesis simulation 32 symbols for hdl files 32 synthesis netlist generation 32 test bench generation 32 design entry 32 design impl...

Страница 104: ...104 ProASIC3 E Starter Kit User s Guide and Tutorial Index V VHDL APA design flow 31 W WaveFormer Lite 41 waveforms 42 web based technical support 101...

Страница 105: ......

Страница 106: ...76 609 300 Fax 44 0 1276 607 540 Actel Japan EXOS Ebisu Building 4F 1 24 14 Ebisu Shibuya ku Tokyo 150 Japan Phone 81 03 3445 7671 Fax 81 03 3445 7668 www jp actel com Actel Hong Kong Room 2107 China...

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