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Step 2 – Perform Pre-Synthesis Simulation
ProASIC3/E Starter Kit User’s Guide and Tutorial 41
Figure 7-10. Design Hierarchy and File Manager Tabs
4. Check the HDL in the file before you continue. In the Design Hierarchy or File Manager tab ( Figure 7-10 ), right-
click count8.vhd and select Check HDL file. This checks the syntax of the count8.vhd file. Before moving to the
next section, modify the code if you find any errors.
The rest of the source code is in the /src folder. Right-click Top.vhd in the design hierarchy and select Set As Root
so that Top.vhd is represented as the top
-
level file for the project. You can import all the files from the Libero IDE
menu, using File > Import Files ( Figure 7-11 ).
Figure 7-11. Import Source Files
Step 2 – Perform Pre-Synthesis Simulation
The next step is simulating the RTL description of the design. First, use WaveFormer Lite to create a stimulus for the
design and then generate a testbench for the design.
Create Stimulus Using WaveFormer Lite
WaveFormer Lite generates VHDL testbenches from drawn waveforms. There are three basic steps for creating
testbenches using WaveFormer Lite and the Actel Libero IDE software:
1. Import Signal Information