Actel ProASIC3/E, Руководство пользователя, Страница: 32 / 106

Actel VHDL ProASIC3/E Design Flow
32 ProASIC3/E Starter Kit User’s Guide and Tutorial
Design Entry
Design entry consists of capturing a schematic representation of the design and performing functional simulations with
a test bench.
Design Capture
For schematic capture, Libero uses ViewDraw® for Actel, which includes a schematic editor. The schematic editor
provides a graphical entry method to capture designs. ViewDraw for Actel is the Libero IDE integrated schematic entry
vehicle, supporting mixed mode entry in which HDL blocks and schematic symbols can be mixed.
The ViewDraw wir file is automatically created after using the Save + Check command in ViewDraw. This file is used
to create the structural HDL netlist.
For more information on using ViewDraw for Actel, refer to the Libero User’s Guide.
Adding ACTgen Macros
Use the ACTgen Macro Builder to instantly create customized macros and then use ViewDraw to add these macros to a
schematic. Alternatively, add the ACTgen Macros in the HDL file.
Creating and Adding Symbols for HDL Files
Schematic users can encapsulate a HDL block into a block symbol.
To create a symbol:
1. Right-click the block in the Design Hierarchy window of Libero IDE.
2. Click Create Symbol . Libero IDE generates a symbol for the selected HDL block.
The macro is accessible from the components list in ViewDraw for Actel.
Test Bench Generation
It is necessary to create a test bench and associate it with a project in order to run a simulation. WaveFormer Lite™ from
SynaptiCAD™ is the Libero IDE integrated test bench generator. WaveFormer Lite fits perfectly into the Libero IDE,
automatically extracting signal information from HDL design files, and producing HDL test bench code that can be
used with any standard VHDL or Verilog simulator.
WaveFormer Lite generates VHDL and Verilog test benches from drawn waveforms.
Pre-Synthesis Simulation
Functional simulation verifies that the logic of a design is functionally correct. Simulation is performed using the Libero
IDE integrated simulator, ModelSim for Actel, which is a custom edition of ModelSim PE that is integrated into the
Libero IDE. ModelSim for Actel is an OEM edition of Model Technology Incorporated (MTI) tools. ModelSim for
Actel supports VHDL or Verilog, but it can only simulate one language at a time. It only works with Actel libraries and
is supported by Actel.
Synthesis & Netlist Generation
After entering the design source, synthesize it to generate a netlist. Synthesis transforms the behavioral HDL source
into a gate-level netlist and optimizes the design for a target technology.
For more detailed information on the above topics, refer to the Libero User’s Guide.