VPX6600
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 26 -
http://www.acromag.com
- 26 -
https://www.acromag.com
3.10 General I/O
3.10.1 General Purpose I/O (GPIO)
The VPX6600 supports 6 GPIO pins which are directly connected to the PCH's
GPIO pins. The direction is software configurable. The GPIO pins are available
on the P2 VPX backplane connector. The GPIO pins are 3.3V level signals.
3.10.2 SMBus
Table 3.10.2.a:
SMBus/I2C Address
Table
The SMBus is connected directly to the PCH, as well as to other devices on the
module. The SMBus is also connected to the VPX backplane as specified in VITA
46.0 VPX Base Specification.
Refer below to Table 3.10.2.a, SMBus/I2C Address Table, below for additional
information.
SMBus ADDR
Function
0x32
DIMMA TEMP
0x34
DIMMA TEMP
0x5A
NCT6016 Super-I/O
0xA0
Acro-Express ID
EEPROM
0xA2
DIMMA SPD
0xA4
DIMMB SPD
0x49
I350 Ethernet
Controller
0x4*
PCA9500 I/O
Expander
0xA*
PCA9500 EEPROM
0x9*
TMP75 Temp
Sensor
Note: Slave addresses of FRU devices (PCA9500, TMP75) are slot dependent
based on VPX Geographical Addressing Bits per VITA 46.
3.10.3 Low Pin Count (LPC)
The LPC interface contains the onboard NTC6106 Super I/O device, which
supplies the two serial ports and also outputs the Port80 Power On Self Test
(POST) codes to the dual 7-segment display.
The onboard Atmel AT97SC3204 TPM device fully integrated security module,
implements version 1.2 of the Trusted Computing Group (TCG) specification for
Trusted Platform Modules (TPM).
