SERIES IP503 INDUSTRIAL I/O PACK EIA/TIA-232E & CENTRONICS COMMUNICATION MODULE
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Interrupt priority is assigned as follows. Initially, with no prior
interrupt history, serial port A has the highest priority and will be
served first, followed by serial port B, then the parallel port.
However, if port A was the last interrupt serviced, then serial port
B will have the highest priority, followed by the parallel port, then
port A, in a last-serviced last-out fashion. Priority shifts in a
similar fashion if serial port B or the parallel port was the last port
serviced. This is useful in preventing continuous interrupts on
one port from freezing out interrupt service for another port
Programming The Parallel Port
This board includes a Centronics parallel-port programmed
via the LEM, LIM, and LPC control registers. These registers
program the extended mode, interrupt source, data direction, and
port signal states for the parallel port. Parallel data is read from
or written to the line printer port data register (LPT)Status
indication for this port is read from the Line Printer Status
Register (LSR)The interrupt vector for the parallel port is stored in
the Line Printer Interrupt Vector Register (LIV)
The line printer port is either output-only (default mode), or bi-
directional depending on the state of extended mode bit (LEM
register) and data direction control pins (bit 5 of the LPC register)
In Normal Mode (Extended Mode bit 0 of LEM register = 0),
reads to the line printer port data register return the last data
written to the port. Write operations output data to the parallel
data lines (PD0-PD7)
In Extended Mode (Extended Mode bit 0 of LEM register = 1),
reads to the line printer port data register will return the last data
written to the port if the data direction bit (bit 5 of the LPC
register) is set low (write), or it will return the data that is present
on PD0-PD7 if the data direction bit is set high (read)Write
operations to the line printer port data register latch data into the
output register, but only drive the parallel data lines (PD0-PD7)
when the data direction bit is set low (write)
PROGRAMMING EXAMPLE
The following example will demonstrate the data transfer
between one serial channel of the host IP503 and another node
using an RTS/CTS protocol. Both nodes will use the FIFO Mode
of operation with a FIFO threshold set at 14 bytes. The data
format will use 8-bit characters, odd-parity, and 1 stop bit. Please
refer to Table 31 for address locations. The “H” following data
refers to the Hexadecimal data format
1 Write 80H to the Line Control Register (LCR)
This sets the Divisor Latch Access bit to permit access to the
two divisor latch bytes used to set the baud rate. These
bytes share addresses with the Receive and Transmit
buffers, and the Interrupt Enable Register (IER)
2 Write 00H to the Divisor Latch MSB (DLM)Write 34H to the
Divisor Latch LSB (DLL)
This sets the divisor to 52 for 9600 baud (i.e. 9600 = 8MHz
÷
[16*52] )
3 Write 0BH to the Line Control Register (LCR)
This first turns off the Divisor Latch Access bit to cause
accesses to the Receiver and Transmit buffers and the
Interrupt Enable Register. It also sets the word length to 8
bits, the number of stop bits to one, and enables odd-parity
4 (OPTIONAL) Write xxH to the Scratch Pad Register
This has no effect on the operation, but is suggested to
illustrate that this register can be used as a 1-byte memory
cell
Alternately, the interrupt vector for the port may be written to
this register and a read will be performed on this register in
response to an interrupt select cycle
5 Write 0FH to the Interrupt Enable Register (IER)
This enables the modem status interrupts and the receiver
line status interrupts. The modem status interrupt is used to
signal changes in CTS* to handle the protocol. The line
status interrupt is used to signal error cases, such as parity or
overrun errors. The modem status interrupts are expected,
but the line status interrupts are not
The received data available and transmit holding buffer
empty interrupts have also been enabled to aide control by
the host CPU in moving data back and forth
6 Write C7H to the FIFO Control Register (FCR)
This enables and initializes the transmit and receive FIFO’s,
and sets the trigger level of the receive FIFO interrupt to 14
bytes
7 Read C1H from the Interrupt Identification Register (IIR)
This is done to check that the device has been programmed
correctly. The upper nibble “C” indicates that the FIFO’s
have been enabled and the lower nibble “1” indicates that no
interrupts are pending
8 Write 02H to the Modem Control Register (MCR)
This sets the Request-To-Send bit and asserts the RTS*
signal line. It is used to signal a receiver that the device is
ready to transmit some data. Note the modem control lines,
either input or output, have no effect on the parallel-to-serial
output data or serial-to-parallel input data. These lines
interact only through CPU control to provide the handshaking
necessary for this data transfer protocol
9 Read 11H from the Modem Status Register (MSR)
This is an indication from the receiver that the Clear-To-Send
signal has been asserted and that there has been a changes
in the CTS* signal since the last read of the MSR.
Consequently, an interrupt will be generated (using
INTREQ0*) to signal the host CPU that it can begin loading
data into the transmit buffer
10 The host should acknowledge the interrupt to clear it, then
begin writing data repeatedly to the Transmitter Holding
Register
