SERIES IP503 INDUSTRIAL I/O PACK EIA/TIA-232E & CENTRONICS COMMUNICATION MODULE
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Line Status Register continued
LSR Bit
FUNCTION
PROGRAMMING
2
Parity Error
(PE)
0 = No Error
1 = Parity Error - the received
character does not have the correct
parity as configured via LCR bits 3
& 4This bit is set high on detection
of a parity error and reset low when
the host CPU reads the contents of
the LSR. In the FIFO mode, the
parity error is associated with a
particular character in the FIFO
(LSR Bit 2 reflects the error when
the character is at the top of the
FIFO)
3
Framing
Error (FE)
0 = No Error
1 = Framing Error - Indicates that
the
received character does not have
a valid stop bit (stop bit following
last data bit or parity bit detected
as a zero/space bit)This bit is
reset low when the CPU reads the
contents of the LSR. In FIFO
Mode, the framing error is
associated with a particular
character in the FIFO (LSR Bit 3
reflects the error when the
character is at the top of the
FIFO)
4
Break
Interrupt (BI)
0 = No Break
1 = Break - the received data input
has been held in the space (logic 0)
state for more than a full-word
transmission time (start bits + data
+ parity bit + stop bits)Reset upon
read of LSR. In FIFO mode, this bit
is associated with a particular
character in the FIFO and reflects
the Break Interrupt when the break
character is at the top of the FIFO.
It is detected by the host CPU
during the first LSR read. Only one
“0” character is loaded into the FIFO
when BI occurs
5
Transmitter
Holding
Register
Empty
(THRE)
0 = Not Empty
1 = Empty - indicates that the
channel is ready to accept a new
character for transmission. Set high
when the character is transferred
from the THR into the transmitter
shift register
Reset low by loading the THR
(It is not reset by a host CPU
read of the LSR)In FIFO
mode, this bit is set when the
Tx FIFO is empty and cleared
when one byte is written to the
Tx FIFO. When a Transmitter
Holding Register Empty
interrupt is enabled by IER bit
1, this signal causes a priority 3
interrupt in the IIR. If the IIR
indicates that this signal is
causing the interrupt, the
interrupt is cleared by a read of
the IIR
Line Status Register continued
LSR Bit
FUNCTION
PROGRAMMING
6
Transmitter
Empty (TEMT)
0 = Not Empty
1 = Transmitter Empty - set when
both the Transmitter Holding
Register (THR) and the
Transmitter Shift Register
(TSR) are both empty. Reset
low when a character is loaded
into the THR and remains low
until the character is
transmitted (it is not reset low
by a read of the LSR)In FIFO
mode, this bit is set when both
the transmitter FIFO and shift
register are empty
7
Receiver FIFO
Error
0 = No Error in FIFO (always 0 in
16C450 mode--FCR bit 0 low)
1 = Error in FIFO - set when one
of
the following data errors is
present in the FIFO: parity
error, framing error, or break
interrupt indication. Cleared by
a host CPU read of the LSR if
there are no subsequent errors
in the FIFO
Note that LSR Bits 1-4 (OE, PE, FE, BI) are the error
conditions that produce a receiver-line-status interrupt (a priority 1
interrupt in the IIR register when any one of these conditions are
detected)This interrupt is enabled by setting IER bit 2 to 1
For the LSR & MSR registers, the setting of the status bits
during a status register read operation is inhibited (the status bit
will not be set until the trailing edge of the read)However, if the
same status condition occurs during a read operation, that status
bit is cleared on the trailing edge of the read instead of being set
again
A power-up or system reset sets all LSR bits to 0, except bits
5 and 6 which are high
MSR - Modem Status Register, Ports A & B (Read/Write)
The Modem Status Register (MSR) provides the host CPU
with an indication on the status of the modem input lines from a
modem or other peripheral device. This register allows the
current state of the four modem input lines (CTS, DSR, RI, and
DCD) to be read (bits 4-7) and provides indication on whether the
states of these lines have changed since the last read of the
MSR (bits 0-3 are set high when the corresponding control inputs
from the modem changes state and are reset low when the CPU
reads the MSR)
MSR - Modem Status Register
MSR BIT
FUNCTION
0
∆
CTS (Set if CTS has changed states since last
read of MSR)
1
∆
DSR (Set if DSR has changed states since last
read of MSR)
2
∆
RI (Trailing Edge Only - Indicates RI* input to the
serial channel has changed state from Low-to-High
since last read of MSR)Not affected by High-to-Low
RI* transitions
3
∆
DCD (Set if DCD has changed states since last
read of MSR)
