SERIES IP521 INDUSTRIAL I/O PACK EIA/TIA-422B SERIAL COMMUNICATION MODULE
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IER BIT
INTERRUPT ACTION
6
1
0 = Disable RTS Interrupt
1 = Enable RTS Interrupt.
This Interrupt is generated when the RTS pin
transitions from a logic 0 to a logic 1. RTS is not
output by this module. Instead RTS is used to enable
the transmitter of the port. This interrupt should always
be disabled.
7
1
0 = Disable CTS Interrupt
1 = Enable CTS Interrupt.
This interrupt will be issued when the CTS pin
transitions from a logic 0 to a logic 1. Since CTS is not
used on this module, this interrupt should always be
disabled.
Notes (Interrupt Enable Register):
1.
Bits 4 to 7 are only programmable when the EFR bit 4 is
set to “1”.
A power-up or system reset sets all IER bits to 0 (bits 7-0 forced
low).
ISR - Interrupt Status Register, Ports A-H (READ Only)
The Interrupt Status Register is used to indicate that a
prioritized interrupt is pending and the type of interrupt that is
pending. Six levels of prioritized interrupts are provided to minimize
software interaction. Performing a read cycle on the ISR will provide
the user with the highest pending interrupt level to be serviced. No
other interrupts are acknowledged until the pending interrupt is
serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. Note, only the current pending interrupt is
cleared by the read. A lower level interrupt may be seen after re-
reading the interrupt status bits.
The eight individual ports share the IP module INTREQ0*
signal. Each port has an opportunity to issue an interrupt in a round
robin fashion. That is, interrupt vectors are served according to a
shifting priority scheme that is a function of the last interrupting port
served.
The following interrupt source table shows the data values (bit 0-
5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
PRIORITY
LEVEL
ISR BITS
Bit5 to Bit0
Source of the Interrupt
1
000110
Receiver Line Status (see LSR bits
1-4)
2
000100
Received Data Ready or Trigger
Level reached.
2
001100
Receive Data Time Out.
3
000010
Transmitter Holding Register
Empty
4
000000
MSR (Modem Status Register)
5
010000
Received Xoff signal special
character
6
100000
CTS, RTS change of state
Note that ISR bit 0 can be used to indicate whether an interrupt
is pending (bit 0 low when interrupt is pending). ISR bits 1 & 2 are
used to indicate the highest priority interrupt pending. ISR bit 3 is
always logic 0 in the 16C450 mode. ISR bit 3 is set along with bit 2
when in the FIFO mode and a timeout interrupt is pending. Bit 4 set
indicates a Xoff/special character detected interrupt pending. Bit 5
indicates a pending interrupt due to a change of state on the CTS or
RTS signals.
Bits 6 and 7 are set when bit 0 of the FIFO Control Register is
set to 1. A power-up or system reset sets ISR bit 0 to logic “1”, and
bits 1 to 7 to logic “0”.
FCR - FIFO Control Register, Ports A-H (WRITE Only)
This write-only register is used to enable and clear the FIFO
buffers, set the transmit/receive FIFO trigger levels, and select the
type of DMA signaling (DMA is NOT supported by this model).
FIFO Control Register
FCR BIT
FUNCTION
0
When set to “1”, this bit enables both the Tx and Rx
FIFO’s. All bytes in both FIFO’s can be cleared by
resetting this bit to 0. Data is cleared automatically
from the FIFO’s when changing from FIFO mode to
the alternate (16C450) mode and visa-versa. This bit
must be a “1” when other FCR bits are written to or
they will not be programmed.
1
When set to “1”, this bit clears all bytes in the Rx-
FIFO and the resets counter logic to 0 (this does not
clear the shift register).
2
When set to “1”, this bit clears all bytes in the Tx-
FIFO and resets the counter logic to 0 (this does not
clear the shift register).
3
When set to “1”, this bit sets DMA Signal from Mode
0 to Mode 1, if FIFO Control Register Bit 0 = 1 (DMA
Not Supported)
5,4
1
These bits are used to set the trigger level for the
transmit FIFO interrupt. An interrupt will be issued
when the number of characters in the FIFO drops
below the selected trigger level. One of four trigger
levels can be selected.
bit 5 bit 4 Trigger Level
0 0 08
0 1 16
1 0 32
1 1 56
7,6
These bits are used to set the trigger level for the
receiver FIFO interrupt. An interrupt is generated
when the number of characters in the FIFO equals
the programmed trigger level. One of four trigger
levels can be selected.
bit 7 bit 6 Trigger Level
0 0 08
0 1 16
1 0 56
1 1 60
Notes (FIFO Control Register):
1.
Bits 4 and 5 are only programmable when the EFR bit 4 is
set to “1”.
A power-up or system reset sets all FCR bits to 0.
