SERIES IP521 INDUSTRIAL I/O PACK EIA/TIA-422B SERIAL COMMUNICATION MODULE
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DLL & DLM - Divisor Latch Registers, Ports A-H (R/W)
The Divisor Latch Registers form the divisor used by the internal
baud-rate generator to divide the 14.7456MHz clock to produce an
internal sampling clock suitable for synchronization to the desired
baud rate. The output of the baud generator (RCLK) is sixteen times
the baud rate. Two 8-bit divisor latch registers per port are used to
store the divisors in 16-bit binary format. The DLL register stores
the low-order byte of the divisor, DLM stores the high-order byte.
These registers must be loaded during initialization.
Note that bit 7 of the LCR register must first be set high to
access the divisor latch registers (DLL & DLM).
Upon loading either latch, a 16-bit baud counter is immediately
loaded (this prevents long counts on initial load). The clock may be
divided by any divisor from 1 to 2
(16-1)
. The relationship between the
baud rate, the divisor, and the 14.7456MHz clock can be
summarized in the following equations:
(
)
Divisor = 14.7456MHz
16
Baud Rate
MCRDIV
×
×
(
)
Baud Rate = 14.7456MHz
16
Divisor
MCRDIV
×
×
The MCRDIV term represents the state of bit-7 of the MCR
(Mode Control Register) as follows:
MCRDIV = 1 If MCR bit-7=0
MCRDIV = 4 If MCR bit-7=1
The following table shows the correct divisor to use for
generation of some standard baud rates (based on the 14.7456MHz
clock). A different external crystal can replace the 14.7456MHz
crystal on the circuit board to obtain unique clock rates. You may
contact Acromag Applications Engineering to explore options in this
area.
Table 3.2: Baud Rate Divisors (
14.7456MHz Clock)
BAUD RATE
DIVISOR (N)
MCR
Bit-7=1
MCR
Bit-7=0
Decimal
DLM
(HEX)
DLL
(HEX)
50
200
4608
12
00
300
1200
768
03
00
600
2400
384
01
80
1200
4800
192
00
C0
2400
9600
96
00
60
3600
14,400
64
00
40
4800
19,200
48
00
30
7200
28,800
32
00
20
9600
38,400
24
00
18
19,200
76,800
12
00
0C
28,800
115,200
8
00
08
38,400
153,600
6
00
06
57,600
230,400
4
00
04
230,400
921,600
1
00
01
With respect to this device, the baud rate may be considered
equal to the number of bits transmitted per second (bps). The bit
rate (bps), or baud rate, defines the bit time. This is the length of
time a bit will be held on before the next bit is transmitted. A receiver
and transmitter must be communicating at the same bit rate, or data
will be garbled. A receiver is alerted to an incoming character by the
start bit, which marks the beginning of the character. It then times
the incoming signal, sampling each bit as near to the center of the
bit time as possible.
To better understand the asynchronous timing used by this
device, note that the receive data line (RxD) is monitored for a high-
to-low transition (start bit). When the start bit is detected, a counter
is reset and counts the 16x sampling clock to 7-1/2 (the center of the
start bit). The receiver then counts from 0 to 15 to sample the next
bit near its center, and so on, until a stop bit is detected, signaling
the end of the data stream. Use of a sampling rate 16x the baud
rate reduces the synchronization error that builds up in estimating
the center of each successive bit following the start bit. As such, if
the data on RxD is a symmetrical square wave, the center of each
successive data cell will occur within
±
3.125% of the actual center
(this is 50%
÷
16, providing an error margin of 46.875%). Thus, the
start bit can begin as much as one 16x clock cycle prior to being
detected.
IER - Interrupt Enable Register, Ports A-H (R/W)
The Interrupt Enable Register is used to independently enable/
disable the serial port interrupt sources. Each of the eight ports
have seven unique interrupt sources which are all mapped to
INTREQ0* of the IP module.
Interrupts are disabled by resetting the corresponding IER bit
low (0), and enabled by setting the IER bit high (1). Disabling the
interrupt system (IER bits 7-5 and 3-0 low) also inhibits the Interrupt
Status Register (ISR) and the interrupt request line (INTREQ0*).
In
addition to enabling the desired bits in the IER, bit-3 of the
Modem Control Register (MCR) must be set to a logic “1” to
enable interrupts.
Interrupt Enable Register
IER BIT
INTERRUPT ACTION
0
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued when the FIFO has
reached the programmed trigger level or is cleared
when the FIFO drops below the trigger level in the
FIFO mode of operation. Note that the receive FIFO
must also be enabled via bit-0 of the FCR for a receive
interrupt to be issued.
1
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued whenever the THR is
empty and is associated with bit-1 in the LSR.
2
0 = Disable Interrupt 1 = Enable Interrupt
This interrupt will be issued whenever a fully
assembled receive character is available.
3
0 = Disable Interrupt 1 = Enable Interrupt
Modem Status Interrupt. Since the modem input
signals are not used on this module, this interrupt
should always be disabled.
4
1
0 = Disable Sleep Mode 1 = Enable Sleep Mode
The clock/oscillator circuit is disabled in sleep mode.
The UART will not lose the programmed bits when
sleep mode is activated or deactivated. The UART will
not enter sleep mode if any interrupts are pending.
5
1
0 = Disable the Receive Xoff Interrupt
1 = Enable the Receive Xoff Interrupt
When software flow control in enabled, and one or two
sequential receive data characters match the
preprogrammed Xoff 1-2 values an interrupt will be
issued.
