SERIES IP521 INDUSTRIAL I/O PACK EIA/TIA-422B SERIAL COMMUNICATION MODULE
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P2 pin assignments are unique to each IP model (see Table 2.1)
and normally correspond to the pin numbers of the field I/O interface
connector on the carrier board (you should verify this for your carrier
board).
Table 2.1: IP521 Field I/O Pin Connections (P2)
Pin Description
Number
Pin Description
Number
COMMON
1
COMMON
26
TXD-_A
2
TXD-_F
27
TXD+_A
3
TXD+_F
28
RXD-_A
4
RXD-_F
29
RXD+_A
5
RXD+_F
30
COMMON
6
COMMON
31
TXD-_B
7
TXD-_G
32
TXD+_B
8
TXD+_G
33
RXD-_B
9
RXD-_G
34
RXD+_B
10
RXD+_G
35
COMMON
11
COMMON
36
TXD-_C
12
TXD-_H
37
TXD+_C
13
TXD+_H
38
RXD-_C
14
RXD-_H
39
RXD+_C
15
RXD+_H
40
COMMON
16
COMMON
41
TXD-_D
17
No Connection
42
TXD+_D
18
No Connection
43
RXD-_D
19
No Connection
44
RXD+_D
20
No Connection
45
COMMON
21
No Connection
46
TXD-_E
22
No Connection
47
TXD+_E
23
No Connection
48
RXD-_E
24
No Connection
49
RXD+_E
25
No Connection
50
In Table 2.1, a suffix of “_A”, “_B”, “_C”, to “_H” is appended to
each pin label to denote its port association. A brief description of
each of the serial port signals at P2 is included below. A complete
functional description of all P2 pin functions is included in Section
4.0 (Theory Of Operation).
P2 Pin Signal Descriptions
SIGNAL
DESCRIPTION
RxD_A
to
RxD_H
Receive Data Line Input - This is the receive data
input line. During Loopback Mode, the RxD input is
disabled from the external connection and connected
to the TxD output internally.
TxD_A
to
TxD_H
Transmit Data Line Output - This is the transmit
output data line. In the idle state, this signal line is
held in the mark (logic 1) state. During Loopback
Mode, the TxD output is internally connected to the
RxD input.
Noise and Grounding Considerations
The serial channels of this module are non-isolated and share a
common signal ground connection. Further, the IP521 is non-
isolated between the logic and field I/O grounds since signal
common is electrically connected to the IP module ground.
Consequently, the field interface connections are not isolated from
the carrier board and backplane. Care should be taken in designing
installations without isolation to avoid noise pickup and ground loops
caused by multiple ground connections.
The signal ground connection at the communication ports are
common to the IP interface ground, which is typically common to
safety (chassis) ground when mounted on a carrier board and
inserted in a backplane. As such, be careful not to attach signal
ground to safety ground via any device connected to these ports, or
a ground loop will be produced, and this may adversely affect
operation.
The communication cabling of the P2 interface carries digital
data at a high transfer rate. For best performance, increased signal
integrity, and safety reasons, you should isolate these connections
away from power and other wiring to avoid noise-coupling and
crosstalk interference. EIA/TIA-422B communication distances are
generally limited to less then 4000 feet. Always keep interface
cabling and ground wiring as short as possible for best performance.
IP Logic Interface Connector (P1)
P1 of the IP module provides the logic interface to the mating
connector on the carrier board. This connector is a 50-pin female
receptacle header (AMP 173279-3 or equivalent) which mates to the
male connector of the carrier board (AMP 173280-3 or equivalent).
This provides excellent connection integrity and utilizes gold-plating
in the mating area. Threaded metric M2 screws and spacers are
supplied with the IP module to provide additional stability for harsh
environments (see Drawing 4501-434 for assembly details).
Table 2.2: Standard Logic Interface Connections (P1)
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
An Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC
Logic Lines are NOT USED by this IP Model.
Field and logic side connectors are keyed to avoid incorrect
assembly. The pin assignments of P1 are standard for all IP
modules according to the Industrial I/O Pack Specification (see
Table 2.2). Note that the IP521 does not utilize all of the logic
signals defined for the P1 connector and these are indicated in
BOLD ITALICS
.
