SERIES IP521 INDUSTRIAL I/O PACK EIA/TIA-422B SERIAL COMMUNICATION MODULE
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When the receiver FIFO and receiver interrupts are enabled, the
following receiver FIFO character time-out status conditions apply:
1. A FIFO character time-out interrupt occurs if:
•
A minimum of one character is in the FIFO.
•
The last received serial character is longer than four
continuous prior character times ago (if 2 stop bits are
programmed, the second one is included in the time delay).
•
The last CPU read of the FIFO is more than four
continuous character times earlier. At 300 baud, and with
12-bit characters (including start, stop, and parity bits), the
FIFO time-out interrupt causes a latency of 160ms
maximum from received character to interrupt issued.
2. From the clock signal input, the character times can be
calculated. The delay is proportional to the baud rate.
3. The time-out timer is reset after the CPU reads the receiver
FIFO or after a new character is received when there has been
no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the
CPU reads a character from the receiver FIFO.
When the transmit FIFO and transmit interrupts are enabled
(FCR Bit 0 = 1 and IER=01), a transmitter interrupt will occur as
follows:
1. When the transmitter FIFO is empty, the transmitter holding
register interrupt (ISR=02) occurs. The interrupt is cleared
when the Transmitter Holding Register (THR) is written to or the
Interrupt Status Register (ISR) is read. One to 128 characters
can be written to the transmit FIFO when servicing this interrupt.
2. The transmit FIFO empty indications are delayed one character
time minus the last stop bit time when the following occurs: Bit 5
of the LSR (THRE) is 1 and there is not a minimum of two bytes
at the same time in the transmit FIFO since the last time
THRE=1. The first transmitter interrupt after changing FCR Bit
0 is immediate, assuming it is enabled.
The receiver FIFO trigger level and character time-out interrupts
have the same priority as the received data-available interrupt. The
Transmitter Holding-Register Empty interrupt has the same priority
as the Transmitter FIFO-Empty interrupt.
Loopback Mode Operation
This device can be operated in a “loopback mode”, useful for
troubleshooting a serial channel without physically wiring to the
channel. Bit 4 of the Modem Control Register (MCR) is used to
program the local loopback feature for the UART channel. When
set high, the UART channel’s serial output line (Transmit Data Path)
is set to the marking (logic 1 state), and the UART receiver serial
data input lines are disconnected from the RxD receiver path. The
output of the UART transmitter shift register is then looped back into
the receiver shift register input. Thus, a write to the Transmitter
Holding Register is automatically looped back to the corresponding
Receiver Buffer Register. The RTS modem control output (of the
MCR Register) is internally connected to the corresponding modem
control input (monitored via the Modem Status Register), while their
associated pins are forced to their high/inactive state. Thus, in
loopback diagnostic mode, transmitted data is immediately received
permitting the host processor to verify the transmit and receive data
paths of the selected serial channel. Further, modem status
interrupt generation is controlled manually in loopback mode by
controlling the state of CTS internally.
Interrupt Generation
This model provides individual control for generation of transmit,
receive, line status, and data set interrupts on each of eight
channels. Each channel shares interrupt request line 0 (INTREQ0)
according to a unique priority shifting scheme that prevents the
continuous interrupts of one channel from freezing out another
channels’ interrupt requests.
After pulling the INTREQ0 line low and in response to an
Interrupt Select cycle, the current highest priority interrupt channel
will serve its interrupt vector first. Interrupt serving priority will shift
as a function of the last port served. A unique interrupt vector may
be assigned to each communication port and is loaded into the
Scratch Pad Register (SCR) for the port. The IP module will thus
execute a read of the scratch pad register in response to an interrupt
select cycle. Two wait states are required to complete this cycle.
Interrupt priority is assigned as follows. Initially, with no prior
interrupt history, Port A has the highest priority and will be served
first, followed by port B, followed by port C etc. to Port H. However,
if port A was the last interrupt serviced, then port B will have the
highest priority, followed by port C, etc. to Port H, then port A, in a
last-serviced last-out fashion. Priority continues to shift in the same
fashion if Port B or Port C was the last interrupt serviced. This is
useful in preventing continuous interrupts on one channel from
freezing out interrupt service for other channels.
Software Flow Control
Model IP521-64 modules include support for software flow
control. Software flow control utilizes special XON & XOFF
characters to control the flow of data, for more efficient data transfer
and to minimize overrun errors.
Software flow control (sometimes called XON/XOFF pacing)
sends a signal from one node to another by adding flow control
characters to the data stream. The receiving node will detect the
XON or XOFF character and respond by suspending transmission
of data (XOFF turns the data flow off), or resuming transmission of
data (XON turns the data flow on). Flow control is used frequently in
data communications to prevent overrun errors or the loss of data.
For example, a node might transmit the XOFF character to the host
computer if the host is sending data too quickly to be processed or
buffered, thus preventing the loss of data.
The flow control characters are stored in the XON-1,2 and
XOFF-1,2 registers. Two XON & XOFF registers are provided
because the flow control character may be 1 or 2 bytes long. The
contents of the XON-1,2 and XOFF-1,2 registers are reset to “0”
upon power-up or system reset, and may be programmed to any
value for software flow control. Different conditions may be set to
detect the XON/XOFF characters or start/stop the transmission.
When software flow control is enabled, the UART of this model
will compare two sequential received data bytes with preprogrammed
XOFF-1,2 characters. When an XOFF match is detected, the
UART will halt transmission after completing the transmission of the
current character. The receive ready flag of the Interrupt Status
register will be set (ISR bit 4 is set to “1” when the XOFF character
has been detected), only if enabled via bit 5 of the Interrupt Enable
register (IER bit 5 is used to enable the received XOFF interrupt)
and bit-3 of the MCR. An interrupt will then be generated. After
