SERIES IP521 INDUSTRIAL I/O PACK EIA/TIA-422B SERIAL COMMUNICATION MODULE
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MSR - Modem Status Register, Ports A-H (Read/Write)
The Modem Status Register (MSR) provides the host CPU with
an indication on the status of the modem input line from a modem or
other peripheral device. However for this model, the four modem
control inputs (CTS, DSR, DCD, and RI) are disconnected from
their receiver input paths.
Modem Status Register
MSR BIT
FUNCTION
0
∆
CTS - NOT SUPPORTED
1
∆
DSR - NOT SUPPORTED
2
∆
RI - NOT SUPPORTED.
3
∆
DCD - NOT SUPPORTED
4
CTS - If the channel is in the loopback mode (MCR
bit 4 = 1), then the state of RTS in the MCR is
reflected.
5
DSR - NOT SUPPORTED
6
RI - NOT SUPPORTED
7
DCD - NOT SUPPORTED
An Asterisk (*) is used to indicate an active-low signal.
Note that reading MSR clears the delta-modem status indication
(bit 0), but has no effect on the bit-4 status bit. For both the LSR &
MSR, the setting of the status bits during a status register read
operation is inhibited (the status bit will not be set until the trailing
edge of the read). However, if the same status condition occurs
during a read operation, that status bit is cleared on the trailing edge
of the read instead of being set again.
Note that not all UART signal paths are used by this model and
their corresponding UART pins are tied high (+5V). This includes,
CTS (Clear To Send), RI (Ring Indicator), DSR (Data Set Ready),
and DCD (Data Carrier Detect).
A power-up or system reset sets MSR bit-0 to “0” (bit 4 is
determined by the corresponding input signal). All other bits are not
used.
SCR - Scratch Pad/Interrupt Vector Register, Ports A-H
(Read/Write)
This 8-bit read/write register has no effect on the operation of
either serial channel. It is provided as an aide to the programmer to
temporarily hold data. Alternately, it stores the interrupt vector for
the port.
In response to an interrupt select cycle, the IP module will
execute a read of this register for the interrupting port (see Interrupt
Generation section for more details).
Enhanced Register Set, Ports A-H
The Enhanced Register Set is unique to the EXAR
UART
provided on the IP521 IP module. The EXAR
UART maintains
compatibility with the industry standard 16C554/654 and
68C554/654 UARTs and provides new features to enhance serial
communication operation.
The new features provided by the EXAR 16C654 UART are
summarized in the following register descriptions and includes
software flow control via Xon and Xoff.
The Enhanced Register Set includes the following registers.
•
Enhanced Feature Register (EFR)
•
Xon-1,
Xon-2
•
Xoff-1,
Xoff-2
In order to access the Enhanced Registers the LCR must be set to
“BF” hex. Each of these registers will be described in the following.
EFR - Enhanced Feature Register, Ports A-H (Read/Write)
The Enhanced Feature register is used to enable or disable
enhanced features, including software flow control. This register is
also used to unlock access to programming the extended register
functionality of IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7.
Enhanced Feature Register
EFR Bit
FUNCTION
PROGRAMMING
3-0
Software
Flow Control
00XX = No Transmit Flow Control
10XX = Transmit Xon1/Xoff1
01XX = Transmit Xon2/Xoff2
11XX = Transmit Xon1 and Xon2,
Xoff1 and Xoff2
XX00 = No receive Flow Control
XX10 = Receiver Compares
Xon1/Xoff1
XX01 = Receiver Compares
Xon2/Xoff2
1011 = Transmit Xon1/Xoff1, Receiver
compares Xon1 and Xon2,
Xoff1 and Xoff2.
0111 = Transmit Xon2/Xoff2. Receiver
compares Xon1 and Xon2,
Xoff1 and Xoff2.
1111 = Transmit Xon1 and Xon2, Xoff1
and Xoff2; Receiver compares
Xon1 and Xon2, Xoff1 and
Xoff2.
0011 = No transmit flow control.
Receiver compares Xon1 and
Xon2, Xoff1 and Xoff2.
4
Enhanced
Function
Control
0 = Disable and latch the Enhanced
Functions: the IER bits 4-7, ISR
bits 4-5, FCR bits 4-5, MCR bits
5-7. This feature prevents existing
software from altering or
overwriting the enhanced
functions.
1 = Enables the enhanced functions.
Allows the IER bits 4-7, ISR bits 4-
5, FCR bits 4-5, and MCR bits
5-7 to be modified.
5
Special
Character
Detect
Control
0 = Disable special character detect.
1 = Enable special character detect.
Incoming receive characters are
compared with Xoff-2 data. If a
match exists, the receive data will
be transferred to FIFO and ISR bit-
4 will be set to indicate detection of
special character. Bit-0 of the
Xoff/Xon registers corresponds
with the LSB bit for the receive
character. When this feature is
enabled, the normal software flow
control must be disabled (EFR bits
0-3 must be
set to a logic “0”).
