SERIES IP320 INDUSTRIAL I/O PACK 12-BIT HIGH DENSITY ANALOG INPUT BOARD
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In Table 2.5, channel designations are abbreviated to save
space. For example, single-ended channel 0 is abbreviated as
"SCH00"; the +input for differential channel 0 is abbreviated as
"+DCH00". Both of these labels are attached to pin 1, but only one
applies according to whether the input is single-ended or differential
(i.e. if your inputs are applied differentially, follow the differential
channel labeling for each channel's + and - input leads).
Table 2.5: IP320 Field I/O Pin Connections (P2)
Pin Description
Number
Pin Description
Number
SCH00/+DCH00
1
SCH32/-DCH12
26
SCH20/-DCH00
2
SCH13/+DCH13
27
SCH01/+DCH01
3
SCH33/-DCH13
28
SCH21/-DCH01
4
SCH14/+DCH14
29
SCH02/+DCH02
5
SCH34/-DCH14
30
SCH22/-DCH02
6
SCH15/+DCH15
31
SCH03/+DCH03
7
SCH35/-DCH15
32
SCH23/-DCH03
8
SCH16/+DCH16
33
SCH04/+DCH04
9
SCH36/-DCH16
34
SCH24/-DCH04
10
SCH17/+DCH17
35
SCH05/+DCH05
11
SCH37/-DCH17
36
SCH25/-DCH05
12
SCH18/+DCH18
37
SCH06/+DCH06
13
SCH38/-DCH18
38
SCH26/-DCH06
14
SCH19/+DCH19
39
SCH07/+DCH07
15
SCH39/-DCH19
40
SCH27/-DCH07
16
SENSE
41
SCH08/+DCH08
17
SENSE
42
SCH28/-DCH08
18
COMMON
43
SCH09/+DCH09
19
COMMON
44
SCH29/-DCH09
20
RESERVED
45
SCH10/+DCH10
21
RESERVED
46
SCH30/-DCH10
22
-15V DC
47
SCH11/+DCH11
23
*Ext Trigger
48
SCH31/-DCH11
24
+15V DC
49
SCH12/+DCH12
25
SHIELD
50
* Indicates an Active-Low Signal.
Analog Input Noise and Grounding Considerations
Differential inputs require two leads (+ and -) per channel, and
provide rejection of common mode voltages. This allows the desired
signal to be accurately measured. However, the signal being
measured cannot be floating--it must be referenced to analog
common on the IP module and be within the normal input voltage
range.
Differential inputs are the best choice when the input channels
are sourced from different locations having slightly different ground
references. See Drawing 4501-435 for analog input connections for
differential and single-ended inputs.
Single-ended inputs only require a single lead (+) per channel,
with a shared "sense" (reference) lead for all channels, and can be
used when a large number of input channels come from the same
location (e.g. printed circuit board). The channel density doubles
when using single-ended inputs, and this a powerful incentive for
their use. However, caution must be exercised since the single
"sense" lead references all channels to the same common which will
induce noise and offset if they are different.
The IP320 is non-isolated, since there is electrical continuity
between the logic and field I/O grounds. As such, the field I/O
connections are not isolated from the carrier board and backplane.
Care should be taken in designing installations without isolation to
avoid noise pickup and ground loops caused by multiple ground
connections. This is particularly important for analog inputs when a
high level of accuracy/resolution is needed (12-bits or more).
Contact your Acromag representative for information on our many
isolated signal conditioning products that could be used to interface
to the IP320 input module.
External Trigger Input
The external trigger signal on P2 is an active-low input which
may be used for synchronizing the ADC conversion of analog inputs
from several IP modules to external events. The external trigger
must be a 5 Volt logic, TTL-compatible, debounced signal
referenced to analog common. The conversion is triggered on the
falling edge of a normally high signal.
The trigger pulse must be low for a minimum of 250nS to
guarantee acquisition. It must not stay low for more than 5uS, or
additional, unwanted acquisitions may be triggered. See Section 3
for programming information.
IP Logic Interface Connector (P1)
The pin assignments of P1 are standard for all IP modules
according to the Industrial I/O Pack Specification (see Table 2.6).
Note that the IP320 does not utilize all of the logic signals defined for
the P1 connector. Logic lines NOT USED used by this model are
indicated in BOLD ITALICS.
Table 2.6: Standard Logic Interface Connections (P1)
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by this IP Model.
