SERIES IP320 INDUSTRIAL I/O PACK 12-BIT HIGH DENSITY ANALOG INPUT BOARD
___________________________________________________________________________________________
- 13 -
Input Overvoltage Protection.........
±
32 Volts with power applied,
±
20 Volts unpowered.
Input Resistance...........................1000 M
Ω
, Typical.
Input Bias Current.........................1nA Typical.
Common Mode Rejection Ratio.....71dB Typical, 60Hz.
CH-to-CH Rejection Ratio.............71 dB Typical, 60Hz.
Resistance to RFI.........................Error is less than
±
0.25% of FSR
with field strengths up to 10V/m at
frequencies of 27MHz, 159MHz,
460MHz.
A/D Resolution..............................12-bits.
Data Format (left-justified)............Bipolar: Bipolar Offset Binary
(BOB); Unipolar: Unipolar Straight
Binary (USB).
No Missing Codes........................No Missing Codes Over
Temperature, 12-bits.
A/D Integral Linearity Error...........
±
1/2 LSB Maximum.
System Accuracy (See Note 4)....The maximum corrected (i.e.
calibrated) error is summarized in
the following table as the worst
case accuracy possible for each
range. It is the sum of error
components due to ADC
quantization of the low and high
calibration signals, PGA and ADC
linearity error, and the absolute
errors of the recommended
calibration voltages at 25oC.
Typical accuracies are significantly
better.
Maximum Overall Calibrated Error @ 25
°°°°
C
Input Range
(Volts)
PGA
Gain
ADC Range
(Volts)
Max Error
±±±±
LSB (% Span)
-5 to +5
1
-5 to +5
1.8 (0.044)
-2.5 to +2.5
2
"
2.1 (0.051)
-1.25 to +1.25
4
"
2.5 (0.061)
-0625 to +0.625
8
"
2.9 (0.071)
-10 to +10
1
-10 to +10
2.8 (0.069)
-5 to +5
2
"
1.8 (0.044)
-2.5 to +2.5
4
"
2.1 (0.051)
-1.25 to +1.25
8
"
2.5 (0.061)
0 to +10
1
0 to +10
3.2 (0.078)
0 to +5
2
"
2.2 (0.055)
0 to +2.5
4
"
3.1 (0.076)
0 to +1.25
8
"
5.1 (0.125)
Settling Time (10V step)........8.5uS to 0.01% of FSR.
A/D Conversion Time.............8.5uS Maximum (includes S/H
acquisition).
A/D Triggers..........................External and Software.
Maximum Throughput Rate...100K conversions/second Maximum
(with 10 uS per conversion/read in
pipelined mode).
Input Noise............................0.2 LSB rms, Typical (with PGA
Gain = 1).
Temperature Coefficient........See specification of calibration
voltages.
Notes:
2. Range assumes the programmable gain is equal to one.
Additional ranges are created with other gains. Divide the listed
range by the programmable gain to determine the actual input
range. Input signal ranges may actually fall short of reaching
the specified endpoints due to hardware limitations. For
example, if an input may reach zero volts or less, a bipolar input
range should be selected.
3. These ranges can only be achieved with
±
15 Volt external power
supplies. The input ranges will be clipped if
±
12 Volt supplies
are used, typically to
±
9 Volt maximum inputs.
4. Follow the input connection recommendations of Section 2,
because input noise and non-ideal grounds can degrade overall
system accuracy. For critical applications multiple input
samples can be averaged to improve performance. Accuracy is
specified for the software conversion command. Use of the
external hardware trigger input with software polling may
degrade accuracy. Accuracy versus temperature depends on
the temperature coefficient of the calibration voltage.
Programmable Calibration Voltages follow:
Calib.
Signal
Ideal
Value
(Volts)
Maximum
Tolerance
@25oC (Volts)
Max
Temperature
Drift (ppm/oC)
Auto Zero
0.0000
±
0.0002
0
CAL0
4.9000
±
0.0005
±
15
CAL1
2.4500
±
0.0005
±
20*
CAL2
1.2250
±
0.0004
"
CAL3
0.6125
±
0.0002
"
* Worst case temperature drift is the sum of the
±
15 ppm/oC
drift of the calibration voltage reference, plus the
±
5 ppm/oC
drift of the resistors in the voltage divider.
INDUSTRIAL I/O PACK COMPLIANCE
Specification.................................This module meets or exceeds all
written Industrial I/O Pack
specifications per revision 0.7.1.
Electrical/Mechanical Interface.....Single-Size IP Module.
IP Data Transfer Cycle Types Supported:
Input/Output (IOSel*).............16-bit word read of 12-bit left-
justified ADC data; 16-bit
read/write of control register;
conversion request (write).
ID Read (IDSel*)....................32 x 8 ID PROM read on D0..D7.
Access Times (8MHz Clock):
ID PROM Read......................0 wait states (250ns cycle).
Control Register Read............0 wait states (250ns cycle).
Control Register Write............1 wait state (375ns cycle).
Conversion Request (Write)...0 wait states (250ns cycle).
Read ADC Data (Note 5)........3 wait states (625ns cycle).
Note:
5. The 3 wait states specified assumes that the previous
conversion has been completed, and that data is available to be
read. If a conversion is in progress, the command will institute
wait states until the data can be delivered. This could take up to
8.5uS, maximum.
