SERIES IP236 INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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to ID space provides the identification for the individual module
(as given in Table 3.1) per the IP specification. Read and write
accesses to the I/O space provide a means to control the IP236.
Access to both ID and I/O spaces are implemented with zero
wait states read or write data transfers, except for write access to
the FIFO buffers. Write cycles to the FIFO buffers requires two
wait states typically and four wait states worst case.
Four wait state writes to the FIFO buffers will only be
implemented when the write overlaps with a FIFO read for DAC
update. The FIFO read operation will wait for a previously started
FIFO write operation without causing the FIFO write to take more
than the typical two wait states. The FIFO read will commence
immediately after the write has completed. If a new write is
required immediately after the previous write then this new write
will be implemented with 4 wait states.
CONVERSION CONTROL LOGIC
All logic to control data conversions is imbedded in the IP
module’s FPGA. The control logic of the IP236 is responsible for
controlling the user specified mode of operation. Once the IP
module has been configured, the control logic performs the
following:
•
Controls serial transfer of data from the FPGA to the
corresponding DAC register based on the selected mode
of operation.
•
Provides external or internal trigger control.
•
Controls read and write access to calibration memory.
•
Controls issue of interrupt requests to the carrier.
•
Provides status on FIFO Full or Almost Empty conditions.
DATA TRANSFER FROM FPGA TO DACs
A 16-bit serial shift register is implemented in the IP module’s
FPGA for each of the supported channels. Internal FPGA
counters are used to synchronize the transfer of FIFO data to the
corresponding serial shift register for output to its converter.
INTERVAL TIMER
Each channel of the IP236 has its own dedicated interval
timer logic. The DAC update interval maybe controlled by the
interval timer, which is a 24-bit counter implemented in the
FPGA. The timer is implemented via two programmable
counters: an 8-bit Timer Prescaler and a 16-bit Conversion Timer.
The Timer Prescaler is clocked by the 8MHz board clock. The
output of the Timer Prescaler is then used to clock the
Conversion Timer. In this way, the two counters are cascaded to
provide variable time periods anywhere from 6.6
µ
seconds to
2.0889 seconds. The output of this interval counter is used to
trigger the start of new conversions. Triggers generated by the
interval counter are also referenced as hardware timer generated
triggers in chapter 3 of this manual.
EXTERNAL TRIGGER
The external trigger connections are made via pins 42 to 49
of the P2 Field I/O Connector. For all modes of operation, when
the external trigger input is enabled via bit 3 of the channel’s
control register, the falling edge of the external trigger will initiate
conversions for the corresponding channel. For External Trigger
Input mode (bit 3 set to digital value “0”), each falling edge of the
external trigger causes a conversion at the DAC. Once the
external trigger signal has been driven low, it should remain low
for a minimum of 250n seconds for proper external trigger
operation. The external trigger input signals must be TTL
compatible. The IP236 uses a diode clamping circuit to protect
the board from external trigger signals that violate the 5 volt logic
(TTL) requirement.
As an output, an active-low TTL signal is driven from the
IP236. The trigger pulse generated is low for 500n seconds
typically. See section 3.0 for programming details to make use of
this signal.
INTERRUPT CONTROL LOGIC
The IP236 can be configured to generate an interrupt on a
programmable FIFO Almost Empty status. When the FIFO has
64, 16, or 4 samples or less left (user programmable) the IP
interrupt signal INTREQ0* is issued to the carrier to request an
interrupt. An 8-bit interrupt service routine vector is provided
during an interrupt acknowledge cycle on data lines D0 to D7.
The interrupt is released when the FIFO is no longer almost
empty or if interrupts are disabled.
CALIBRATION MEMORY CONTROL LOGIC
The FPGA of the IP236 module contains control logic that
implements read and write access to calibration memory. The
calibration memory (EEPROM) contains offset and gain
coefficients for each of the ranges and channels. Calibration of
the individual DACs is implemented via software to avoid the
mechanical drawbacks of hardware potentiometers.
IP Module Software
Acromag also provides a software diskette (sold separately)
of IP module Object Linking and Embedding (OLE) drivers for
Windows 95
/NT
compatible application programs (Model
IPSW-OLE-PCI, MSDOS format). This software provides
individual drivers that allow all IP modules and the APC8620
carrier to be easily integrated into Windows
application
programs, such as Visual C++
, Visual Basic
, Borland
Delphi
, Microsoft
Office
97 applications and others. The
OLE controls provide a high-level interface to IP modules,
eliminating the need to perform low-level reads/writes of
registers, and the writing of interrupt handlers—all the
complicated details of programming are handled by the OLE
controls. These functions are intended for use in conjunction with
an Acromag personal computer carrier and consist of a carrier
OLE control, and an OLE control for each Acromag IP module as
well as a generic OLE control for non-Acromag IP modules.
In addition, Acromag provides a software product (sold
separately) consisting of IP module VxWorks
drivers. This
software (Model IPSW-API-VXW MSDOS format) is composed of
VxWorks
(real time operating system) libraries for all Acromag
IP modules and carriers including the AVME9660/9630,
APC8610, and APC8620. The software is implemented as a
library of “C” functions which when linked with existing user code
makes possible simple control of all Acromag IP modules and
carriers.
