SERIES IP236 INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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ANALOG OUTPUTS
Output Channels……………… IP236-8 Eight Independent
Single Ended Channels
IP236-4 Four Independent Single
Ended Channels
Output Signal Type................... Voltage (Non-isolated).
Output Ranges
2
………………..
(Jumper Selected)
Bipolar -5 to +5 Volts
Bipolar -10 to +10 Volts
Unipolar 0 to +10 Volts
Note:
2. The actual outputs may fall short of the range endpoints due
to hardware offset and gain errors. The software calibration
corrects for these across the output range, but cannot extend
the output beyond that achievable with the hardware.
Output Current…………………. -5mA to +5mA (Maximum); this
corresponds to a minimum load
resistance of 2K
Ω
with a 10V
output.
DAC Data Format……………… Positive-true binary two’s
complement (BTC) input codes.
DAC Programming................… Independent; Input registers and
FIFOs are directly loaded
Resolution............................…. 16-bits.
Monotonicity over Temperature 16-bits (IP236)
15-bits (IP236E)
Linearity Error........................... + 2 LSB (Maximum).
Differential Linearity Error......... + 1 LSB (Maximum).
Maximum Overall Calibrated Error
3,4
Max. Linearity
Error LSB
Max. Offset
Error LSB
Max. Gain
Error LSB
Max. Total
Error LSB
(%)
±
2
±
1
±
1
±
4 (0.0061)
Note:
3. Offset and gain calibration coefficients stored in the
coefficient memory must be used to perform software
calibration in order to achieve the specified accuracy.
Specified accuracy does not include quantization error and
are with outputs unloaded. Follow the output connection
recommendations of Chapter 2, to keep non-ideal grounds
from degrading overall system accuracy.
4. The maximum uncalibrated error combining the linearity,
offset and gain errors is
±
0.453%.
DAC714HL @ 25oC:
Linearity Error is
±
0.003% maximum (i.e.
±
2 LSB).
Bipolar Offset Error is
±
0.2% FSR (i.e. 20V SPAN) max.
Gain Error is
±
0.25% maximum.
Settling Time.............................10uS to within 0.003% of FSR for
a 20V step change (load of 5K
Ω
in parallel with 500pF).
Conversion Rate (per channel). 150KHz Maximum,
100KHz recommended for
specified accuracy.
Output Noise………………….... 120 nV/
√
Hz typical
Output at Reset.........................Bipolar Zero Volts.
Unipolar 5 Volts (See Note 5)
Board Warm-up Time............... 8 minutes minimum
Note:
5. The hardware reset function resets the DAC analog output
and the FPGA’s internal DAC FIFO buffer. The software
reset will only clear the FPGA’s internal DAC FIFO buffer. A
software reset has no affect on the DAC analog output.
Output Impedence.................... 0.1
Ω
Typical at 25oC
Short Circuit Protection ............ Indefinite at 25oC.
FIFO Buffer…………………….. 128 Samples per Channel
Interrupt…………………………. Vectored interrupt on Almost
Empty Condition.
External Trigger Input/Output
As An Input:..................….....… Negative edge triggered. Must
be an active low 5 volt logic TTL
compatible, debounced signal
referenced to digital common.
Conversions are triggered within
6.4u seconds of the falling edge.
Minimum pulse width is 250n
seconds.
As An Output…………............. Active low 5 volt logic TTL
compatible output is generated.
The trigger pulse is low for
typically 500n seconds.
INDUSTRIAL I/O PACK COMPLIANCE
Specification………….………… This device meets or exceeds all
written Industrial I/O Pack
specifications per ANSI/VITA 4
1995 for 8MHz operation for
Format I Modules.
Electrical/Mechanical
Interface………………….……...
Single-Size IP Module.
I/O Space Read/Write.…....…...16-bit, 8-bit:
ID Space Read.........…........…. 16-bit, 8-bit (low byte) Supports
Type 1, 32 bytes per IP
(consecutive odd byte
addresses).
Memory Space....................…. Not Used.
Interrupts……................……… 8-bits (low byte)
Generates INTREQ0* interrupt
request per IP and interrupt
acknowledge cycles via access
to IP INT space.
Access Times (8MHz Clock):
ID Space Read...........….…...…0 wait state (250ns cycle).
FIFO Buffer Write…..….……... 2 wait states typical (500ns),
5-wait states maximum (875ns)
Registers Read/Write…….…... 0 wait state (250ns cycle).
Interrupt Read/Write…...……... 0 wait states (250ns cycle).
