SERIES IP236 INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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connector. Conversions are performed for the corresponding
channel, independent of all other channels, with each external
trigger pulse. The interval between conversions is controlled by
the period between external triggers. The interval timer has no
functionality in this mode of operation.
Note that the external trigger signal must be configured as an
input for this mode of operation. Bit-3 of the Channel Control
register must be set to a logic “0”.
External Trigger Only mode of operation can be used to
synchronize multiple IP236 modules to a single module running in
a continuous conversion mode. The external trigger, of the IP236
“master”, must be programmed as an output. The external trigger
signal of that IP236 must then be connected to the external
trigger signal of all other IP236 modules, programmed for
external trigger input, that are to be synchronized. These other
IP236 modules must be programmed for External Trigger Input
only mode. Data conversion can then be started by writing high
to the Start Convert bit of the master IP236 configured for
continuous conversion mode.
PROGRAMMING CONSIDERATIONS
The IP236 provides different methods of analog output
generation to give the user maximum flexibility for each
application. Examples are presented in the following sections to
illustrate programming the different modes of operation.
Single Conversion Mode Example
This example will enable channel 0 for the single conversion
mode of operation. The conversion can be initiated via software
or external trigger.
1. Execute Write of 0002H to the Control Register at Base
A 08H.
a) Single Conversion from FIFO buffer is enabled.
b) External, and Software generated triggers are enabled.
2. Execute Write of 7FFFH to the FIFO buffer port at Base
A 0CH. This will drive channel zero’s analog output
to plus full scale minus one least significant bit.
3. Execute Write 0001H to the Start Convert Bit at Base
A 00H. This starts the transfer of the digital data in
channel zero’s FIFO buffer to its corresponding converter for
analog conversion.
Continuous Conversion Mode with Interrupt Example
This example will enable channel 7 for continuous conversion
mode of operation. Interrupts are enabled and an interrupt
threshold of 16 samples is enabled. The interval timer will be set
for an 80
µ
second interval. The conversions can be initiated via
software or external trigger.
This example assumes that the IP236 is installed onto an
Acromag AVME9630/60 carrier board (consult your carrier board
documentation for compatibility details).
1.
Clear the global interrupt enable bit in the carrier board
status register by writing a “0” to bit 3.
2.
Write the interrupt vector to the IP236 Module at base
a 03H.
3.
Write to the carrier board interrupt Level Register to program
the desired interrupt level per bits 2,1, & 0.
4.
Write “1” to the carrier board IP Interrupt Clear Register
corresponding to the desired IP interrupt request being
configured.
5.
Write “1” to the carrier board IP Interrupt Enable Register bit
corresponding to the IP interrupt request to be enabled.
6.
Enable interrupts for the carrier board by writing a “1” to bit 3
(the Global Interrupt Enable Bit) of the carrier board’s Status
Register.
7.
Execute Write of 54H to the Channel Control Register at
Base A 33H.
a)
Continuous Conversion mode is selected.
b)
External, Software, and Hardware timer generated
triggers are all enabled.
c)
Interrupts are enabled.
d)
Interrupt when 16 or less values remain in the FIFO
buffer.
8.
Execute Write of 50H to Timer Prescaler Register at Base
A 32H.
a)
This sets the Timer Prescaler to 80 decimal.
9.
Execute Write of 0008H to the Conversion Timer Register at
Base A 34H. The conversion timer in conjunction
with the Timer Prescaler sets the interval time between
conversions to (80
∗
8)
÷
8 = 80
µ
seconds.
10. Execute Write of 8000H to the FIFO buffer port at Base
A 36H. Channel 7’s first FIFO location is written
with digital value 8000H. This digital value will provide a
minus full scale analog output when converted. Continue to
fill the FIFO with 127 additional values.
11. Execute Write of 0080H to the Start Convert Bit at Base
A 00H. This starts the transfer of data from
channel seven’s FIFO buffer to its corresponding DAC for
analog conversions. Conversions will continue with interrupt
request when 16 or fewer samples reside in the FIFO buffer.
General Sequence of Events for Processing an Interrupt
1.
The IP236 asserts the Interrupt Request 0 Line (INTREQ0*)
in response to an interrupt condition.
2.
The AVME9630/60 carrier board acts as an interrupter in
making the VMEbus interrupt request (IRQx*) corresponding
to the IP interrupt request.
3.
The VMEbus host (interrupt handler) asserts IACK* and the
level of the interrupt it is seeking on A01-A03.
4.
When the asserted VMEbus IACKIN* signal (daisy-chained)
is passed to the AVME9630/60, the carrier board will check
if the level requested matches that specified by the host. If
it matches, the carrier board will assert the INTSEL* line to
the appropriate IP together with (carrier board generated)
address bit A1 to select which interrupt request is being
processed (A1 low corresponds to INTREQ0*).
5.
The IP236 puts the interrupt vector on the local data bus
(D00-D07 for the D08 [O] interrupter) and asserts ACK* to
the carrier board. The carrier board passes this along to the
VMEbus (D08[O]) and asserts DTACK*.
