SERIES IP236 INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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Table 2.3: IP236
2
Field I/O Pin Connections (P2)
Pin Description
Number
Pin Description
Number
+CH00
1
No Connection
26
-CH00
1
2
No Connection
27
COMMON
1
3
No Connection
28
+CH01
4
No Connection
29
-CH01
1
5
No Connection
30
COMMON
1
6
No Connection
31
+CH02
7
No Connection
32
-CH02
1
8
No Connection
33
COMMON
1
9
No Connection
34
+CH03
10
No Connection
35
-CH03
1
11
No Connection
36
COMMON
1
12
No Connection
37
+CH04
13
No Connection
38
-CH04
1
14
No Connection
39
COMMON
1
15
No Connection
40
+CH05
16
No Connection
41
-CH05
1
17
EXT TRIGCH0*
42
COMMON
1
18
EXT TRIG CH1*
43
+CH06
19
EXT TRIG CH2*
44
-CH06
1
20
EXT TRIG CH3*
45
COMMON
1
21
EXT TRIG CH4*
46
+CH07
22
EXT TRIG CH5*
47
-CH07
1
23
EXT TRIG CH6*
48
COMMON
1
24
EXT TRIGCH7*
49
No Connection
25
SHIELD
50
Notes:
1. The minus leads of all channels are connected to analog
common on the module.
2. Channels 04 through 07 are only present on 8 channel
models.
Analog Outputs: Noise and Grounding Considerations
All output channels are referenced to analog common on the
module (See Drawing 4501-737 for analog output connections),
but each channel has a separate return (minus lead) to maintain
accuracy and reduce noise. Still, the accuracy of the voltage
output depends on the amount of current loading (impedance of
the load) and the length (impedance) of the cabling. High
impedance loads (e.g. loads > 100K
Ω
) provide the best accuracy.
For low impedance loads, the IP236 can source up to 5mA, but
the effects of source and cabling resistance should be
considered.
Output common is electrically connected to the IP module
analog ground which connects to logic ground of the module at
the DAC’s. As such, the IP236 is non-isolated between the logic
and field I/O grounds. Consequently, the field I/O connections
are not isolated from the carrier board and backplane. Care
should be taken in designing installations without isolation to
avoid noise pickup and ground loops caused by multiple ground
connections. This is particularly important for analog outputs
when a high level of accuracy/resolution is needed. Refer to
Drawing 4501-737 for example output and grounding
connections.
External Trigger Input/Output Signals
The external trigger signals on pins 42 to 49 of the P2
connector can be programmed to accept a TTL compatible
external trigger input signal, or output hardware timer generated
triggers to allow synchronization of multiple IP236 modules.
As an input, the external trigger must be a 5 Volt logic, TTL-
compatible, debounced signal referenced to analog common.
The trigger pulse must be low for a minimum of 250n seconds to
guarantee acquisition. The actual conversion is triggered within
6.25
µ
seconds of the falling edge of the external trigger signal.
This type of conversion triggering can be used to synchronize
generation of analog output signals to external events.
As an output an active-low TTL signal can be driven to
additional IP236 modules, thus providing a means to synchronize
conversions. The additional IP236 modules must be
programmed for external trigger input and convert on external
trigger only mode. The trigger pulse generated is low for 500n
seconds, typically. See section 3.0 for programming details to
make use of this signal.
IP Logic Interface Connector (P1)
P1 of the IP module provides the logic interface to the mating
connector on the carrier board. This connector is a 50-pin female
receptacle header (AMP 173279-3 or equivalent) which mates to
the male connector of the carrier board (AMP 173280-3 or
equivalent). This provides excellent connection integrity and
utilizes gold-plating in the mating area. Threaded metric M2
screws and spacers are supplied with the IP module to provide
additional stability for harsh environments (see Drawing 4501-434
for assembly details). Field and logic side connectors are keyed
to avoid incorrect assembly. The pin assignments of P1 are
standard for all IP modules according to the Industrial I/O Pack
Specification (see Table 2.4).
Table 2.4: Standard Logic Interface Connections (P1)
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
An Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC
Logic Lines are NOT USED by this IP Model.
