AP512 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 31 - http://www.acromag.com
- 31 -
https://www.acromag.com
transmitter FIFO and shift register are empty.
7
Receiver
FIFO Error
0 = No Error in FIFO (it is always 0
in 16C450 mode--FCR bit 0 low).
1 = Error in FIFO - set when one of the following
data errors is present in the FIFO: parity error,
framing error, or break interrupt indication.
Cleared by a host CPU read of the LSR if there are
no subsequent errors in the FIFO. FIFO read of
offending character is also required.
Note that LSR Bits 1-4 (OE, PE, FE, BI) are the error conditions that produce a
receiver-line-status interrupt (a priority 1 interrupt in the ISR register when
any one of these conditions are detected). This interrupt is enabled by
setting IER bit 2 to “1”.
A power-up or system reset sets all LSR bits to 0, except bits 5 and 6 which
are high.
3.2.11 MSR - Modem Status Register (Read/Write)
The Modem Status Register (MSR) provides the host CPU with an indication
on the status of the modem input line from a modem or other peripheral
device. This register allows the current state of CTS to be read (bit 0) and
provides indication on whether the states of the lines has changed since the
last read of the MSR (bit 0 is set high when the corresponding control input
changes state and is reset low when the CPU reads the MSR).
For the AP512 model, the four modem control inputs (CTS, DSR, DCD, and
RI) are disconnected from their receiver input paths.
Table 3.12 Modem Status
Register
MSR
BIT
FUNCTION
0
CTS - CTS (Set if CTS* has changed states since last read of
MSR)
1
DSR - NOT SUPPORTED
2
RI - NOT SUPPORTED.
3
DCD - NOT SUPPORTED
4
CTS - If the channel is in the loopback mode (MCR bit 4 = 1),
then the state of RTS in the MCR is reflected.
5
DSR - NOT SUPPORTED
